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| author | Philipp Tomsich <philipp.tomsich@vrull.eu> | 2021-10-06 22:26:46 +0200 |
|---|---|---|
| committer | Nelson Chu <nelson.chu@sifive.com> | 2021-10-07 17:09:25 +0800 |
| commit | 9455c91957590ca6d4520cfe0955f9f9f1349f82 (patch) | |
| tree | aad247fc0afd07817c5ebeb29f95b28a1e9015be /include | |
| parent | 586dcfc81ee4a24c150362c624a47d633e4d6bdc (diff) | |
| download | binutils-9455c91957590ca6d4520cfe0955f9f9f1349f82.zip binutils-9455c91957590ca6d4520cfe0955f9f9f1349f82.tar.gz binutils-9455c91957590ca6d4520cfe0955f9f9f1349f82.tar.bz2 | |
RISC-V: Add support for Zbs instructions
This change adds the Zbs instructions from the Zbs 1.0.0 specification.
See
https://github.com/riscv/riscv-bitmanip/releases/tag/1.0.0
for the frozen specification.
2021-01-09 Philipp Tomsich <philipp.tomsich@vrull.eu>
bfd/
* elfxx-riscv.c (riscv_supported_std_z_ext): Added zbs.
gas/
* config/tc-riscv.c (riscv_multi_subset_supports): Handle INSN_CLASS_ZBS.
* testsuite/gas/riscv/b-ext.d: Test Zbs instructions.
* testsuite/gas/riscv/b-ext.s: Likewise.
* testsuite/gas/riscv/b-ext-64.d: Likewise.
* testsuite/gas/riscv/b-ext-64.s: Likewise.
include/
* opcode/riscv-opc.h: Added MASK/MATCH/DECLARE_INSN for Zbs.
* opcode/riscv.h (riscv_insn_class): Added INSN_CLASS_ZBS.
opcodes/
* riscv-opc.c (riscv_supported_std_z_ext): Add zbs.
Signed-off-by: Philipp Tomsich <philipp.tomsich@vrull.eu>
Diffstat (limited to 'include')
| -rw-r--r-- | include/opcode/riscv-opc.h | 24 | ||||
| -rw-r--r-- | include/opcode/riscv.h | 1 |
2 files changed, 25 insertions, 0 deletions
diff --git a/include/opcode/riscv-opc.h b/include/opcode/riscv-opc.h index 9999da6..45a207d 100644 --- a/include/opcode/riscv-opc.h +++ b/include/opcode/riscv-opc.h @@ -495,6 +495,22 @@ #define MASK_CLMULH 0xfe00707f #define MATCH_CLMULR 0xa002033 #define MASK_CLMULR 0xfe00707f +#define MATCH_BCLRI 0x48001013 +#define MASK_BCLRI 0xfc00707f +#define MATCH_BSETI 0x28001013 +#define MASK_BSETI 0xfc00707f +#define MATCH_BINVI 0x68001013 +#define MASK_BINVI 0xfc00707f +#define MATCH_BEXTI 0x48005013 +#define MASK_BEXTI 0xfc00707f +#define MATCH_BCLR 0x48001033 +#define MASK_BCLR 0xfe00707f +#define MATCH_BSET 0x28001033 +#define MASK_BSET 0xfe00707f +#define MATCH_BINV 0x68001033 +#define MASK_BINV 0xfe00707f +#define MATCH_BEXT 0x48005033 +#define MASK_BEXT 0xfe00707f #define MATCH_FLW 0x2007 #define MASK_FLW 0x707f #define MATCH_FLD 0x3007 @@ -1102,6 +1118,14 @@ DECLARE_INSN(slli_uw, MATCH_SLLI_UW, MASK_SLLI_UW) DECLARE_INSN(clmul, MATCH_CLMUL, MASK_CLMUL) DECLARE_INSN(clmulh, MATCH_CLMULH, MASK_CLMULH) DECLARE_INSN(clmulr, MATCH_CLMULR, MASK_CLMULR) +DECLARE_INSN(bclri, MATCH_BCLRI, MASK_BCLRI) +DECLARE_INSN(bseti, MATCH_BSETI, MASK_BSETI) +DECLARE_INSN(binvi, MATCH_BINVI, MASK_BINVI) +DECLARE_INSN(bexti, MATCH_BEXTI, MASK_BEXTI) +DECLARE_INSN(bclr, MATCH_BCLR, MASK_BCLR) +DECLARE_INSN(bset, MATCH_BSET, MASK_BSET) +DECLARE_INSN(binv, MATCH_BINV, MASK_BINV) +DECLARE_INSN(bext, MATCH_BEXT, MASK_BEXT) DECLARE_INSN(flw, MATCH_FLW, MASK_FLW) DECLARE_INSN(fld, MATCH_FLD, MASK_FLD) DECLARE_INSN(flq, MATCH_FLQ, MASK_FLQ) diff --git a/include/opcode/riscv.h b/include/opcode/riscv.h index a8f4741..afcd41f 100644 --- a/include/opcode/riscv.h +++ b/include/opcode/riscv.h @@ -319,6 +319,7 @@ enum riscv_insn_class INSN_CLASS_ZBA, INSN_CLASS_ZBB, INSN_CLASS_ZBC, + INSN_CLASS_ZBS, }; /* This structure holds information for a particular instruction. */ |