diff options
| author | Alice Carlotti <alice.carlotti@arm.com> | 2025-04-07 20:21:07 +0100 |
|---|---|---|
| committer | Alice Carlotti <alice.carlotti@arm.com> | 2025-05-09 20:19:30 +0100 |
| commit | 92f7d4ddde6de117ecbd677dcfa87ac4f7e9f43b (patch) | |
| tree | 69ab4610ebe75b95592f9881e3e412fb0e49f3a9 /include | |
| parent | 4250bea744bdd373ba82b237ef7b1e77570f3fb3 (diff) | |
| download | binutils-92f7d4ddde6de117ecbd677dcfa87ac4f7e9f43b.zip binutils-92f7d4ddde6de117ecbd677dcfa87ac4f7e9f43b.tar.gz binutils-92f7d4ddde6de117ecbd677dcfa87ac4f7e9f43b.tar.bz2 | |
aarch64: Eliminate AARCH64_OPND_SVE_ADDR_R
Adjust parsing for AARCH64_OPND_SVE_ADDR_RR{_LSL*} operands to accept
implicit XZR offsets. Add new AARCH64_OPND_SVE_ADDR_RM{_LSL*} operands
to support instructions where an XZR offset is allowed but must be
specified explicitly. This allows the removal of the duplicate opcode
table entries using AARCH64_OPND_SVE_ADDR_R.
Diffstat (limited to 'include')
| -rw-r--r-- | include/opcode/aarch64.h | 16 |
1 files changed, 10 insertions, 6 deletions
diff --git a/include/opcode/aarch64.h b/include/opcode/aarch64.h index dfe3f05..df90bb7 100644 --- a/include/opcode/aarch64.h +++ b/include/opcode/aarch64.h @@ -704,12 +704,16 @@ enum aarch64_opnd AARCH64_OPND_SVE_ADDR_RI_U6x2, /* SVE [<Xn|SP>, #<uimm6>*2]. */ AARCH64_OPND_SVE_ADDR_RI_U6x4, /* SVE [<Xn|SP>, #<uimm6>*4]. */ AARCH64_OPND_SVE_ADDR_RI_U6x8, /* SVE [<Xn|SP>, #<uimm6>*8]. */ - AARCH64_OPND_SVE_ADDR_R, /* SVE [<Xn|SP>]. */ - AARCH64_OPND_SVE_ADDR_RR, /* SVE [<Xn|SP>, <Xm|XZR>]. */ - AARCH64_OPND_SVE_ADDR_RR_LSL1, /* SVE [<Xn|SP>, <Xm|XZR>, LSL #1]. */ - AARCH64_OPND_SVE_ADDR_RR_LSL2, /* SVE [<Xn|SP>, <Xm|XZR>, LSL #2]. */ - AARCH64_OPND_SVE_ADDR_RR_LSL3, /* SVE [<Xn|SP>, <Xm|XZR>, LSL #3]. */ - AARCH64_OPND_SVE_ADDR_RR_LSL4, /* SVE [<Xn|SP>, <Xm|XZR>, LSL #4]. */ + AARCH64_OPND_SVE_ADDR_RR, /* SVE [<Xn|SP>{, <Xm|XZR>}]. */ + AARCH64_OPND_SVE_ADDR_RR_LSL1, /* SVE [<Xn|SP>{, <Xm|XZR>, LSL #1}]. */ + AARCH64_OPND_SVE_ADDR_RR_LSL2, /* SVE [<Xn|SP>{, <Xm|XZR>, LSL #2}]. */ + AARCH64_OPND_SVE_ADDR_RR_LSL3, /* SVE [<Xn|SP>{, <Xm|XZR>, LSL #3}]. */ + AARCH64_OPND_SVE_ADDR_RR_LSL4, /* SVE [<Xn|SP>{, <Xm|XZR>, LSL #4}]. */ + AARCH64_OPND_SVE_ADDR_RM, /* SVE [<Xn|SP>, <Xm|XZR>]. */ + AARCH64_OPND_SVE_ADDR_RM_LSL1, /* SVE [<Xn|SP>, <Xm|XZR>, LSL #1]. */ + AARCH64_OPND_SVE_ADDR_RM_LSL2, /* SVE [<Xn|SP>, <Xm|XZR>, LSL #2]. */ + AARCH64_OPND_SVE_ADDR_RM_LSL3, /* SVE [<Xn|SP>, <Xm|XZR>, LSL #3]. */ + AARCH64_OPND_SVE_ADDR_RM_LSL4, /* SVE [<Xn|SP>, <Xm|XZR>, LSL #4]. */ AARCH64_OPND_SVE_ADDR_RX, /* SVE [<Xn|SP>, <Xm>]. */ AARCH64_OPND_SVE_ADDR_RX_LSL1, /* SVE [<Xn|SP>, <Xm>, LSL #1]. */ AARCH64_OPND_SVE_ADDR_RX_LSL2, /* SVE [<Xn|SP>, <Xm>, LSL #2]. */ |