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| author | Christoph Müllner <christoph.muellner@vrull.eu> | 2023-07-03 12:10:47 +0200 |
|---|---|---|
| committer | Nelson Chu <nelson@rivosinc.com> | 2023-07-03 18:17:59 +0800 |
| commit | 704b30cbb2beeac1e90c4ee6f1f5b9f1dc2e5ee4 (patch) | |
| tree | b05368971f51c38351e0044d3b9199254bc75e02 /include | |
| parent | d501d384886673b7c3981fe225b2d7719440abda (diff) | |
| download | binutils-704b30cbb2beeac1e90c4ee6f1f5b9f1dc2e5ee4.zip binutils-704b30cbb2beeac1e90c4ee6f1f5b9f1dc2e5ee4.tar.gz binutils-704b30cbb2beeac1e90c4ee6f1f5b9f1dc2e5ee4.tar.bz2 | |
RISC-V: Zvkh[a,b]: Remove individual instruction class
Currently we have three instruction classes defined for Zvkh[a,b]:
- INSN_CLASS_ZVKNHA
- INSN_CLASS_ZVKNHB
- INSN_CLASS_ZVKNHA_OR_ZVKNHB
The encodings of all instructions in Zvknh[a,b] are identical.
Therefore, we don't need the individual instruction classes
and can remove them.
This patch also adds the missing support of the combined instruction
class in riscv_multi_subset_supports_ext().
Fixes: 62edb233ef5 ("RISC-V: Add support for the Zvknh[a,b] ISA extensions")
Reported-By: Nelson Chu <nelson@rivosinc.com>
Signed-off-by: Christoph Müllner <christoph.muellner@vrull.eu>
Diffstat (limited to 'include')
| -rw-r--r-- | include/opcode/riscv.h | 2 |
1 files changed, 0 insertions, 2 deletions
diff --git a/include/opcode/riscv.h b/include/opcode/riscv.h index d859f44..739d6da 100644 --- a/include/opcode/riscv.h +++ b/include/opcode/riscv.h @@ -418,8 +418,6 @@ enum riscv_insn_class INSN_CLASS_ZVBC, INSN_CLASS_ZVKG, INSN_CLASS_ZVKNED, - INSN_CLASS_ZVKNHA, - INSN_CLASS_ZVKNHB, INSN_CLASS_ZVKNHA_OR_ZVKNHB, INSN_CLASS_ZVKSED, INSN_CLASS_ZVKSH, |