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author | Andrew Burgess <andrew.burgess@embecosm.com> | 2018-12-04 11:48:42 +0000 |
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committer | Andrew Burgess <andrew.burgess@embecosm.com> | 2018-12-11 11:36:52 +0000 |
commit | 99e1a184a791d30c09a86d6eca4528dc146c2c79 (patch) | |
tree | a93f9626946d8aec365af5b66891bc5dea60ae54 /gdb/testsuite/gdb.base/float.exp | |
parent | 8970c0224e3c36c565672089e38de42765e87f47 (diff) | |
download | binutils-99e1a184a791d30c09a86d6eca4528dc146c2c79.zip binutils-99e1a184a791d30c09a86d6eca4528dc146c2c79.tar.gz binutils-99e1a184a791d30c09a86d6eca4528dc146c2c79.tar.bz2 |
gdb/riscv: Update test to handle targets without an fpu
The FPU is optional on RISC-V. The gdb.base/float.exp test currently
assumes that an fpu is always available on RISC-V. Update the test so
that this is not the case.
gdb/testsuite/ChangeLog:
* gdb.base/float.exp: Handle RISC-V targets without an FPU.
Diffstat (limited to 'gdb/testsuite/gdb.base/float.exp')
-rw-r--r-- | gdb/testsuite/gdb.base/float.exp | 10 |
1 files changed, 9 insertions, 1 deletions
diff --git a/gdb/testsuite/gdb.base/float.exp b/gdb/testsuite/gdb.base/float.exp index 71d3f60..23d68a13 100644 --- a/gdb/testsuite/gdb.base/float.exp +++ b/gdb/testsuite/gdb.base/float.exp @@ -111,7 +111,15 @@ if { [is_aarch64_target] } then { } elseif [istarget "sparc*-*-*"] then { gdb_test "info float" "f0.*f1.*f31.*d0.*d30.*" "info float" } elseif [istarget "riscv*-*-*"] then { - gdb_test "info float" "ft0.*ft1.*ft11.*fflags.*frm.*fcsr.*" "info float" + # RISC-V may or may not have an FPU + gdb_test_multiple "info float" "info float" { + -re "ft0.*ft1.*ft11.*fflags.*frm.*fcsr.*$gdb_prompt $" { + pass "info float (with FPU)" + } + -re "No floating.point info available for this processor.*$gdb_prompt $" { + pass "info float (without FPU)" + } + } } else { gdb_test "info float" "No floating.point info available for this processor." "info float (unknown target)" } |