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authorChristina Schimpe <christina.schimpe@intel.com>2024-04-11 05:55:01 -0400
committerChristina Schimpe <christina.schimpe@intel.com>2025-08-29 17:02:10 +0000
commita48e55b57081eb14149776f46afb65da2d5966cd (patch)
treef21e4396cd4fb247a89a49809fb0b51cd300be88 /gdb/doc
parent4c2fee0658ea2f279d8eb09f20962f139d9dfec3 (diff)
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gdb: Implement amd64 linux shadow stack support for inferior calls.
This patch enables inferior calls to support Intel's Control-Flow Enforcement Technology (CET), which provides the shadow stack feature for the x86 architecture. Following the restriction of the linux kernel, enable inferior calls for amd64 only. Reviewed-by: Thiago Jung Bauermann <thiago.bauermann@linaro.org> Reviewed-By: Eli Zaretskii <eliz@gnu.org> Approved-By: Luis Machado <luis.machado@arm.com> Approved-By: Andrew Burgess <aburgess@redhat.com>
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diff --git a/gdb/doc/gdb.texinfo b/gdb/doc/gdb.texinfo
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@@ -27037,6 +27037,38 @@ registers
@end itemize
+@subsubsection Intel Control-Flow Enforcement Technology.
+@cindex Intel Control-Flow Enforcement Technology.
+
+The @dfn{Intel Control-Flow Enforcement Technology} (@acronym{Intel CET})
+provides two capabilities to defend against ``Return-oriented Programming''
+and ``call/jmp-oriented programming'' style control-flow attacks:
+
+@itemize @bullet
+@item Shadow Stack:
+A shadow stack is a second stack for a program. It holds the return
+addresses pushed by the call instruction. The @code{RET} instruction pops the
+return addresses from both call and shadow stack. If the return addresses from
+the two stacks do not match, the processor signals a control protection
+exception.
+@item Indirect Branch Tracking (IBT):
+When IBT is enabled, the CPU implements a state machine that tracks
+indirect @code{JMP} and @code{CALL} instructions. The state machine can
+be either IDLE or WAIT_FOR_ENDBRANCH. When a @code{JMP} or @code{CALL} is
+executed the state machine chages to the WAIT_FOR_ENDBRANCH state. In
+WAIT_FOR_ENDBRANCH state the next instruction in the program stream
+must be an @code{ENDBR} instruction, otherwise the processor signals a
+control protection exception. After executing a @code{ENDBR} instruction
+the state machine returns to the IDLE state.
+@end itemize
+
+Impact on Call/Print:
+Inferior calls in @value{GDBN} reset the current PC to the beginning of the
+function that is called. No call instruction is executed, but the @code{RET}
+instruction actually is. To avoid a control protection exception due to the
+missing return address on the shadow stack, @value{GDBN} pushes the new return
+address to the shadow stack and updates the shadow stack pointer.
+
@node Alpha
@subsection Alpha