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| author | Andre Vieira <andre.simoesdiasvieira@arm.com> | 2018-10-31 11:57:38 +0000 |
|---|---|---|
| committer | Andre Vieira <andre.simoesdiasvieira@arm.com> | 2018-10-31 12:11:01 +0000 |
| commit | cd53832b008b25222ec55bf947e3700528ee0814 (patch) | |
| tree | 9a7ba0b03d5fee6b797585013919b06ca1471c34 /gas | |
| parent | b4e093995600e8f482c10467379f9395b4871ca2 (diff) | |
| download | binutils-cd53832b008b25222ec55bf947e3700528ee0814.zip binutils-cd53832b008b25222ec55bf947e3700528ee0814.tar.gz binutils-cd53832b008b25222ec55bf947e3700528ee0814.tar.bz2 | |
[GAS][ARM] Fix failing Armv1 test
This test has been failing for a while and it could be argued that since we
started testing 'arm7t' here (and not Armv1) the test itself was wrong. So I
changed the assembly to Armv1. Given the changes to objdump when
"disassembling all" it seemed like a good idea to force the disassembly to
'armv2' instead and actually accept the disassembly of the 26-bit Architecture
variants of tst, teq, cmn and cmp.
gas/ChangeLog
2018-10-31 Andre Vieira <andre.simoesdiasvieira@arm.com>
* testsuite/gas/arm/armv1.d: Assemble for Armv1 and disassemble for
Armv2.
Diffstat (limited to 'gas')
| -rw-r--r-- | gas/ChangeLog | 5 | ||||
| -rw-r--r-- | gas/testsuite/gas/arm/armv1.d | 36 |
2 files changed, 23 insertions, 18 deletions
diff --git a/gas/ChangeLog b/gas/ChangeLog index bbf6918..41a8d0c 100644 --- a/gas/ChangeLog +++ b/gas/ChangeLog @@ -1,3 +1,8 @@ +2018-10-31 Andre Vieira <andre.simoesdiasvieira@arm.com> + + * testsuite/gas/arm/armv1.d: Assemble for Armv1 and disassemble for + Armv2. + 2018-10-29 Alan Modra <amodra@gmail.com> * Makefile.am (HFILES): Delete struc-symbol.h. diff --git a/gas/testsuite/gas/arm/armv1.d b/gas/testsuite/gas/arm/armv1.d index 8b9759b..ad8fc48 100644 --- a/gas/testsuite/gas/arm/armv1.d +++ b/gas/testsuite/gas/arm/armv1.d @@ -1,6 +1,6 @@ -#objdump: -dr --prefix-addresses --show-raw-insn +#objdump: -dr --prefix-addresses --show-raw-insn -marmv2 #name: ARM v1 instructions -#as: -mcpu=arm7t +#as: -march=armv1 #warning_output: armv1.l # Test the ARM v1 instructions @@ -30,29 +30,29 @@ Disassembly of section .text: 0+4c <[^>]*> e1d00000 ? bics r0, r0, r0 0+50 <[^>]*> e1100000 ? tst r0, r0 0+54 <[^>]*> e1100000 ? tst r0, r0 -0+58 <[^>]*> e110f000 ? tst r0, r0 +0+58 <[^>]*> e110f000 ? tstp r0, r0 0+5c <[^>]*> e1300000 ? teq r0, r0 0+60 <[^>]*> e1300000 ? teq r0, r0 -0+64 <[^>]*> e130f000 ? teq r0, r0 +0+64 <[^>]*> e130f000 ? teqp r0, r0 0+68 <[^>]*> e1500000 ? cmp r0, r0 0+6c <[^>]*> e1500000 ? cmp r0, r0 -0+70 <[^>]*> e150f000 ? cmp r0, r0 +0+70 <[^>]*> e150f000 ? cmpp r0, r0 0+74 <[^>]*> e1700000 ? cmn r0, r0 0+78 <[^>]*> e1700000 ? cmn r0, r0 -0+7c <[^>]*> e170f000 ? cmn r0, r0 -0+80 <[^>]*> e1a00000 ? nop[ ]+\(mov r0,r0\) +0+7c <[^>]*> e170f000 ? cmnp r0, r0 +0+80 <[^>]*> e1a00000 ? nop[\s]+; \(mov r0, r0\) 0+84 <[^>]*> e1b00000 ? movs r0, r0 0+88 <[^>]*> e1e00000 ? mvn r0, r0 0+8c <[^>]*> e1f00000 ? mvns r0, r0 0+90 <[^>]*> ef000000 ? (swi|svc) 0x00000000 -0+94 <[^>]*> e5900000 ? ldr r0, \[r0\] -0+98 <[^>]*> e5d00000 ? ldrb r0, \[r0\] -0+9c <[^>]*> e4b10000 ? ldrt r0, \[r1\] -0+a0 <[^>]*> e4f10000 ? ldrbt r0, \[r1\] -0+a4 <[^>]*> e5800000 ? str r0, \[r0\] -0+a8 <[^>]*> e5c00000 ? strb r0, \[r0\] -0+ac <[^>]*> e4a10000 ? strt r0, \[r1\] -0+b0 <[^>]*> e4e10000 ? strbt r0, \[r1\] +0+94 <[^>]*> e5100000 ? ldr r0, \[r0, #-0\] +0+98 <[^>]*> e5500000 ? ldrb r0, \[r0, #-0\] +0+9c <[^>]*> e4b10000 ? ldrt r0, \[r1\], #0 +0+a0 <[^>]*> e4f10000 ? ldrbt r0, \[r1\], #0 +0+a4 <[^>]*> e5000000 ? str r0, \[r0, #-0\] +0+a8 <[^>]*> e5400000 ? strb r0, \[r0, #-0\] +0+ac <[^>]*> e4a10000 ? strt r0, \[r1\], #0 +0+b0 <[^>]*> e4e10000 ? strbt r0, \[r1\], #0 0+b4 <[^>]*> e8800001 ? stm r0, {r0} 0+b8 <[^>]*> e9800001 ? stmib r0, {r0} 0+bc <[^>]*> e8000001 ? stmda r0, {r0} @@ -69,6 +69,6 @@ Disassembly of section .text: 0+e8 <[^>]*> e8100001 ? ldmda r0, {r0} 0+ec <[^>]*> e9100001 ? ldmdb r0, {r0} 0+f0 <[^>]*> e9900001 ? ldmib r0, {r0} -0+f4 <[^>]*> e1a00000 ? nop[ ]+\(mov r0,r0\) -0+f8 <[^>]*> e1a00000 ? nop[ ]+\(mov r0,r0\) -0+fc <[^>]*> e1a00000 ? nop[ ]+\(mov r0,r0\) +0+f4 <[^>]*> e1a00000 ? nop[\s]+; \(mov r0, r0\) +0+f8 <[^>]*> e1a00000 ? nop[\s]+; \(mov r0, r0\) +0+fc <[^>]*> e1a00000 ? nop[\s]+; \(mov r0, r0\) |