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| author | Andrew Bennett <andrew.bennett@imgtec.com> | 2015-03-13 22:42:55 +0000 |
|---|---|---|
| committer | Andrew Bennett <andrew.bennett@imgtec.com> | 2015-03-13 23:01:34 +0000 |
| commit | 6914869aa73d6cd12121ed6b3e58e1564ef5575d (patch) | |
| tree | e7c200b1ef71953a4a344e88b8e37d421e21119d /gas | |
| parent | 21e20815a20606a858f626e09944f29ee5ebee82 (diff) | |
| download | binutils-6914869aa73d6cd12121ed6b3e58e1564ef5575d.zip binutils-6914869aa73d6cd12121ed6b3e58e1564ef5575d.tar.gz binutils-6914869aa73d6cd12121ed6b3e58e1564ef5575d.tar.bz2 | |
MIPS: Fix constraint issues with the R6 beqc and bnec instructions
opcodes/
* mips-opc.c (decode_mips_operand): Fix constraint issues
with u and y operands.
gas/testsuite/
* gas/mips/mips.exp: Added branch constraints testcase.
* gas/mips/r6-branch-constraints.s: New test.
* gas/mips/r6-branch-constraints.l: New test.
Diffstat (limited to 'gas')
| -rw-r--r-- | gas/testsuite/ChangeLog | 6 | ||||
| -rw-r--r-- | gas/testsuite/gas/mips/mips.exp | 2 | ||||
| -rw-r--r-- | gas/testsuite/gas/mips/r6-branch-constraints.l | 25 | ||||
| -rw-r--r-- | gas/testsuite/gas/mips/r6-branch-constraints.s | 25 |
4 files changed, 58 insertions, 0 deletions
diff --git a/gas/testsuite/ChangeLog b/gas/testsuite/ChangeLog index 1fd7362..0054afd 100644 --- a/gas/testsuite/ChangeLog +++ b/gas/testsuite/ChangeLog @@ -1,5 +1,11 @@ 2015-03-13 Andrew Bennett <andrew.bennett@imgtec.com> + * gas/mips/mips.exp: Added branch constraints testcase. + * gas/mips/r6-branch-constraints.s: New test. + * gas/mips/r6-branch-constraints.l: New test. + +2015-03-13 Andrew Bennett <andrew.bennett@imgtec.com> + * gas/mips/r6.s: Add evp and dvp instructions. * gas/mips/r6.d: Likewise. * gas/mips/r6-n32.d: Likewise. diff --git a/gas/testsuite/gas/mips/mips.exp b/gas/testsuite/gas/mips/mips.exp index 34414e1..11c9b05 100644 --- a/gas/testsuite/gas/mips/mips.exp +++ b/gas/testsuite/gas/mips/mips.exp @@ -1454,4 +1454,6 @@ if { [istarget mips*-*-vxworks*] } { } run_list_test_arches "r6-removed" "-32" [mips_arch_list_matching mips32r6] run_list_test_arches "r6-64-removed" [mips_arch_list_matching mips64r6] + + run_list_test_arches "r6-branch-constraints" [mips_arch_list_matching mips32r6] } diff --git a/gas/testsuite/gas/mips/r6-branch-constraints.l b/gas/testsuite/gas/mips/r6-branch-constraints.l new file mode 100644 index 0000000..819a09a --- /dev/null +++ b/gas/testsuite/gas/mips/r6-branch-constraints.l @@ -0,0 +1,25 @@ +.*: Assembler messages: +.*:2: Error: invalid operands `blezc \$0,.' +.*:3: Error: the source register must not be \$0 `bgezc \$0,.' +.*:4: Error: invalid operands `bgtzc \$0,.' +.*:5: Error: the source register must not be \$0 `bltzc \$0,.' +.*:6: Error: invalid operands `beqzc \$0,.' +.*:7: Error: invalid operands `bnezc \$0,.' +.*:8: Error: invalid operands `bgec \$0,\$2,.' +.*:9: Error: invalid operands `bgec \$2,\$0,.' +.*:10: Error: invalid operands `bgec \$2,\$2,.' +.*:11: Error: invalid operands `bgeuc \$0,\$2,.' +.*:12: Error: invalid operands `bgeuc \$2,\$0,.' +.*:13: Error: invalid operands `bgeuc \$2,\$2,.' +.*:14: Error: invalid operands `bltc \$0,\$2,.' +.*:15: Error: invalid operands `bltc \$2,\$0,.' +.*:16: Error: invalid operands `bltc \$2,\$2,.' +.*:17: Error: invalid operands `bltuc \$0,\$2,.' +.*:18: Error: invalid operands `bltuc \$2,\$0,.' +.*:19: Error: invalid operands `bltuc \$2,\$2,.' +.*:20: Error: invalid operands `beqc \$0,\$2,.' +.*:21: Error: invalid operands `beqc \$2,\$0,.' +.*:22: Error: invalid operands `beqc \$2,\$2,.' +.*:23: Error: invalid operands `bnec \$0,\$2,.' +.*:24: Error: invalid operands `bnec \$2,\$0,.' +.*:25: Error: invalid operands `bnec \$2,\$2,.' diff --git a/gas/testsuite/gas/mips/r6-branch-constraints.s b/gas/testsuite/gas/mips/r6-branch-constraints.s new file mode 100644 index 0000000..62ca893 --- /dev/null +++ b/gas/testsuite/gas/mips/r6-branch-constraints.s @@ -0,0 +1,25 @@ + .text + blezc $0,. + bgezc $0,. + bgtzc $0,. + bltzc $0,. + beqzc $0,. + bnezc $0,. + bgec $0,$2,. + bgec $2,$0,. + bgec $2,$2,. + bgeuc $0,$2,. + bgeuc $2,$0,. + bgeuc $2,$2,. + bltc $0,$2,. + bltc $2,$0,. + bltc $2,$2,. + bltuc $0,$2,. + bltuc $2,$0,. + bltuc $2,$2,. + beqc $0,$2,. + beqc $2,$0,. + beqc $2,$2,. + bnec $0,$2,. + bnec $2,$0,. + bnec $2,$2,. |