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authorRichard Sandiford <richard.sandiford@arm.com>2023-03-30 11:09:10 +0100
committerRichard Sandiford <richard.sandiford@arm.com>2023-03-30 11:09:10 +0100
commit60336e19658f1b820753ac09797f14b26e594cfa (patch)
treefa19c746ec4f0f8639a847697c59a2195f2c8826 /gas
parent4eede8c2442115513a3f0c4f3610fbd6fe919a58 (diff)
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aarch64: Add +sme2
This patch adds bare-bones support for +sme2. Later patches fill in the rest.
Diffstat (limited to 'gas')
-rw-r--r--gas/NEWS2
-rw-r--r--gas/config/tc-aarch64.c2
-rw-r--r--gas/doc/c-aarch64.texi2
3 files changed, 6 insertions, 0 deletions
diff --git a/gas/NEWS b/gas/NEWS
index 4ae2089..05fbed1 100644
--- a/gas/NEWS
+++ b/gas/NEWS
@@ -1,5 +1,7 @@
-*- text -*-
+* Add SME2 support to the AArch64 port.
+
Changes in 2.40:
* Add support for Intel RAO-INT instructions.
diff --git a/gas/config/tc-aarch64.c b/gas/config/tc-aarch64.c
index 2d4c610..6ebfcda 100644
--- a/gas/config/tc-aarch64.c
+++ b/gas/config/tc-aarch64.c
@@ -10183,6 +10183,8 @@ static const struct aarch64_option_cpu_value_table aarch64_features[] = {
AARCH64_FEATURE (AARCH64_FEATURE_SME, 0)},
{"sme-i16i64", AARCH64_FEATURE (AARCH64_FEATURE_SME_I16I64, 0),
AARCH64_FEATURE (AARCH64_FEATURE_SME, 0)},
+ {"sme2", AARCH64_FEATURE (AARCH64_FEATURE_SME2, 0),
+ AARCH64_FEATURE (AARCH64_FEATURE_SME, 0)},
{"bf16", AARCH64_FEATURE (AARCH64_FEATURE_BFLOAT16, 0),
AARCH64_FEATURE (AARCH64_FEATURE_FP, 0)},
{"i8mm", AARCH64_FEATURE (AARCH64_FEATURE_I8MM, 0),
diff --git a/gas/doc/c-aarch64.texi b/gas/doc/c-aarch64.texi
index 3921c0d..acde4a7 100644
--- a/gas/doc/c-aarch64.texi
+++ b/gas/doc/c-aarch64.texi
@@ -235,6 +235,8 @@ automatically cause those extensions to be disabled.
@tab Enable SME F64F64 Extension.
@item @code{sme-i16i64} @tab Armv9-A @tab No
@tab Enable SME I16I64 Extension.
+@item @code{sme2} @tab Armv9-A @tab No
+ @tab Enable SME2. This implies @code{sme}.
@item @code{ssbs} @tab ARMv8-A @tab ARMv8.5-A or later
@tab Enable Speculative Store Bypassing Safe state read and write.
@item @code{sve} @tab ARMv8.2-A @tab Armv9-A or later