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| author | Xiao Zeng <zengxiao@eswincomputing.com> | 2024-06-06 15:59:53 +0800 |
|---|---|---|
| committer | Nelson Chu <nelson@rivosinc.com> | 2024-06-06 16:10:53 +0800 |
| commit | 0b4595be3f04aa3741157b24654e554fc3264fc2 (patch) | |
| tree | 777105142cf7f51e06a3a0ec62d8ffd6dbcb8b96 /gas | |
| parent | d9c14a8744b01b0d3d03a661c732a4d4d5740fbc (diff) | |
| download | binutils-0b4595be3f04aa3741157b24654e554fc3264fc2.zip binutils-0b4595be3f04aa3741157b24654e554fc3264fc2.tar.gz binutils-0b4595be3f04aa3741157b24654e554fc3264fc2.tar.bz2 | |
RISC-V: Add support for Zvfbfwma extension
This implements the Zvfbfwma extension, as of version 1.0.
View detailed information in:
<https://github.com/riscv/riscv-isa-manual/blob/main/src/bfloat16.adoc#zvfbfwma---vector-bf16-widening-mul-add>
1 In spec: "Zvfbfwma requires the Zvfbfmin extension and the Zfbfmin extension."
1.1 In Embedded Processor: Zvfbfwma -> Zvfbfmin -> Zve32f
1.2 In Application Processor: Zvfbfwma -> Zvfbfmin -> V
1.3 In both scenarios, there are: Zvfbfwma -> Zfbfmin
2 Depending on different usage scenarios, the Zvfbfwma extension may
depend on 'V' or 'Zve32f'. This patch only implements dependencies in
scenario of Embedded Processor. This is consistent with the processing
strategy in Zvfbfmin. In scenario of Application Processor, it is
necessary to explicitly indicate the dependent 'V' extension.
For relevant information in gcc, please refer to:
<https://gcc.gnu.org/git/?p=gcc.git;a=commit;h=38dd4e26e07c6be7cf4d169141ee4f3a03f3a09d>
bfd/ChangeLog:
* elfxx-riscv.c (riscv_multi_subset_supports): Handle Zvfbfwma.
(riscv_multi_subset_supports_ext): Ditto.
gas/ChangeLog:
* NEWS: Updated.
* testsuite/gas/riscv/march-help.l: Ditto.
* testsuite/gas/riscv/zvfbfwma.d: New test.
* testsuite/gas/riscv/zvfbfwma.s: New test.
include/ChangeLog:
* opcode/riscv-opc.h (MATCH_VFWMACCBF16_VF): Define.
(MASK_VFWMACCBF16_VF): Ditto.
(MATCH_VFWMACCBF16_VV): Ditto.
(MASK_VFWMACCBF16_VV): Ditto.
(DECLARE_INSN): New declarations for Zvfbfwma.
* opcode/riscv.h (enum riscv_insn_class): Add
INSN_CLASS_ZVFBFWMA
opcodes/ChangeLog:
* riscv-opc.c: Add Zvfbfwma instructions.
Diffstat (limited to 'gas')
| -rw-r--r-- | gas/NEWS | 2 | ||||
| -rw-r--r-- | gas/testsuite/gas/riscv/march-help.l | 1 | ||||
| -rw-r--r-- | gas/testsuite/gas/riscv/zvfbfwma.d | 12 | ||||
| -rw-r--r-- | gas/testsuite/gas/riscv/zvfbfwma.s | 7 |
4 files changed, 22 insertions, 0 deletions
@@ -25,6 +25,8 @@ * Add support for RISC-V Zvfbfmin extension with version 1.0. +* Add support for RISC-V Zvfbfwma extension with version 1.0. + * The base register operand in D(X,B) and D(L,B) may be explicitly omitted in assembly on s390. It can now be coded as D(X,) or D(L,) instead of D(X,0) D(X,%r0), D(L,0), and D(L,%r0). diff --git a/gas/testsuite/gas/riscv/march-help.l b/gas/testsuite/gas/riscv/march-help.l index 38c70e2..dd82752 100644 --- a/gas/testsuite/gas/riscv/march-help.l +++ b/gas/testsuite/gas/riscv/march-help.l @@ -59,6 +59,7 @@ All available -march extensions for RISC-V: zvbb 1.0 zvbc 1.0 zvfbfmin 1.0 + zvfbfwma 1.0 zvfh 1.0 zvfhmin 1.0 zvkb 1.0 diff --git a/gas/testsuite/gas/riscv/zvfbfwma.d b/gas/testsuite/gas/riscv/zvfbfwma.d new file mode 100644 index 0000000..05da132 --- /dev/null +++ b/gas/testsuite/gas/riscv/zvfbfwma.d @@ -0,0 +1,12 @@ +#as: -march=rv64iv_zvfbfwma +#objdump: -d + +.*:[ ]+file format .* + +Disassembly of section .text: + +0+000 <target>: +[ ]+[0-9a-f]+:[ ]+ee865257[ ]+vfwmaccbf16.vf[ ]+v4,fa2,v8 +[ ]+[0-9a-f]+:[ ]+ec865257[ ]+vfwmaccbf16.vf[ ]+v4,fa2,v8,v0.t +[ ]+[0-9a-f]+:[ ]+ee861257[ ]+vfwmaccbf16.vv[ ]+v4,v12,v8 +[ ]+[0-9a-f]+:[ ]+ec861257[ ]+vfwmaccbf16.vv[ ]+v4,v12,v8,v0.t diff --git a/gas/testsuite/gas/riscv/zvfbfwma.s b/gas/testsuite/gas/riscv/zvfbfwma.s new file mode 100644 index 0000000..f824af9 --- /dev/null +++ b/gas/testsuite/gas/riscv/zvfbfwma.s @@ -0,0 +1,7 @@ +target: + # vfwmaccbf16.vf + vfwmaccbf16.vf v4, fa2, v8 + vfwmaccbf16.vf v4, fa2, v8, v0.t + # vfwmaccbf16.vv + vfwmaccbf16.vv v4, v12, v8 + vfwmaccbf16.vv v4, v12, v8, v0.t |