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authorJim Wilson <jimw@sifive.com>2018-05-18 14:03:18 -0700
committerJim Wilson <jimw@sifive.com>2018-05-18 14:03:18 -0700
commit7f99954970001cfc1b155d877ac2966d77e2c647 (patch)
tree585e05cfeb9fc8e287b7b607bc27851b90ebf30c /gas/doc
parent400174b12a46fffbfad7c2504c33bb3ac29f3ef9 (diff)
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RISC-V: Add RV32E support.
Kito Cheng <kito.cheng@gmail.com> Monk Chiang <sh.chiang04@gmail.com> bfd/ * elfnn-riscv.c (_bfd_riscv_elf_merge_private_bfd_data): Handle EF_RISCV_RVE. binutils/ * readelf.c (get_machine_flags): Handle EF_RISCV_RVE. gas/ * config/tc-riscv.c (rve_abi): New. (riscv_set_options): Add rve field. Initialize it. (riscv_set_rve) New function. (riscv_set_arch): Support 'e' ISA subset. (reg_lookup_internal): If rve, check register is available. (riscv_set_abi): New parameter rve. (md_parse_option): Pass new argument to riscv_set_abi. (riscv_after_parse_args): Call riscv_set_rve. If rve_abi, set EF_RISCV_RVE. * doc/c-riscv.texi (-mabi): Document new ilp32e argument. include/ * elf/riscv.h (EF_RISCV_RVE): New define.
Diffstat (limited to 'gas/doc')
-rw-r--r--gas/doc/c-riscv.texi3
1 files changed, 2 insertions, 1 deletions
diff --git a/gas/doc/c-riscv.texi b/gas/doc/c-riscv.texi
index 79bc4e3..045c33a 100644
--- a/gas/doc/c-riscv.texi
+++ b/gas/doc/c-riscv.texi
@@ -46,7 +46,8 @@ Select the base isa, as specified by ISA. For example -march=rv32ima.
Selects the ABI, which is either "ilp32" or "lp64", optionally followed
by "f", "d", or "q" to indicate single-precision, double-precision, or
quad-precision floating-point calling convention, or none to indicate
-the soft-float calling convention.
+the soft-float calling convention. Also, "ilp32" can optionally be followed
+by "e" to indicate the RVE ABI, which is always soft-float.
@cindex @samp{-mrelax} option, RISC-V
@item -mrelax