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| author | Hau Hsu <hau.hsu@sifive.com> | 2024-06-18 14:49:04 +0800 |
|---|---|---|
| committer | Nelson Chu <nelson@rivosinc.com> | 2024-06-18 15:06:34 +0800 |
| commit | 7003edc383feaa72c13310d075d383c2a98a6a6e (patch) | |
| tree | 5c36a828df0eda14aa56dcec63b53455b26b8590 /gas/doc/c-riscv.texi | |
| parent | 88729e96162f0293177d2324fc8dc6cd78aac793 (diff) | |
| download | binutils-7003edc383feaa72c13310d075d383c2a98a6a6e.zip binutils-7003edc383feaa72c13310d075d383c2a98a6a6e.tar.gz binutils-7003edc383feaa72c13310d075d383c2a98a6a6e.tar.bz2 | |
RISC-V: Add SiFive cease extension v1.0
Add SiFive cease extension,
https://sifive.cdn.prismic.io/sifive/767804da-53b2-4893-97d5-b7c030ae0a94_s76mc_core_complex_manual_21G3.pdf
This aligns LLVM:
* https://llvm.org/docs/RISCVUsage.html
* https://github.com/llvm/llvm-project/pull/83896
bfd/ChangeLog:
* elfxx-riscv.c (riscv_supported_vendor_x_ext): Add support for
'xsfcease'.
(riscv_multi_subset_supports): Handle INSN_CLASS_XSFCEASE.
(riscv_multi_subset_supports_ext): Handle INSN_CLASS_XSFCEASE.
gas/ChangeLog:
* doc/c-riscv.texi: Updated.
* testsuite/gas/riscv/march-help.l: Updated.
* testsuite/gas/riscv/sifive-insns.d: Add test case for 'sf.cease'.
* testsuite/gas/riscv/sifive-insns.s: Likewise.
include/ChangeLog:
* opcode/riscv-opc.h (MATCH_SF_CEASE, MASK_SF_CEASE): Define match and
mask encoding for 'sf.cease'.
* opcode/riscv.h (INSN_CLASS_XSFCEASE): Add new instruction class for
'xsfcease'.
opcodes/ChangeLog:
* riscv-opc.c (riscv_opcodes): Add opcode entry for 'sf.cease'.
Diffstat (limited to 'gas/doc/c-riscv.texi')
| -rw-r--r-- | gas/doc/c-riscv.texi | 5 |
1 files changed, 5 insertions, 0 deletions
diff --git a/gas/doc/c-riscv.texi b/gas/doc/c-riscv.texi index 61bb7bc..e579eeb 100644 --- a/gas/doc/c-riscv.texi +++ b/gas/doc/c-riscv.texi @@ -850,4 +850,9 @@ VCIX as a low-latency, high-throughput interface to a coprocessor. It is documented in @url{https://sifive.cdn.prismic.io/sifive/c3829e36-8552-41f0-a841-79945784241b_vcix-spec-software.pdf}. +@item XSfCease +XSfCease provides an instruction to instigates power-down sequence. + +It is documented in @url{https://sifive.cdn.prismic.io/sifive/767804da-53b2-4893-97d5-b7c030ae0a94_s76mc_core_complex_manual_21G3.pdf}. + @end table |