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| author | Alice Carlotti <alice.carlotti@arm.com> | 2025-04-20 23:25:11 +0100 |
|---|---|---|
| committer | Alice Carlotti <alice.carlotti@arm.com> | 2025-05-09 20:27:19 +0100 |
| commit | d34b54505b4cf30898158a6995fcea33448cf00d (patch) | |
| tree | 7d0cc6b5e4b0311b651791764938cff156a02515 | |
| parent | b8fab5284ea586a0c64bc2fa41d52dcc364004d4 (diff) | |
| download | binutils-d34b54505b4cf30898158a6995fcea33448cf00d.zip binutils-d34b54505b4cf30898158a6995fcea33448cf00d.tar.gz binutils-d34b54505b4cf30898158a6995fcea33448cf00d.tar.bz2 | |
aarch64: Add tests for fabd, urecpe and ursqrt
Other instructions in the encoding group are tested in advsimd-fp16.d,
so add these instructions to the existing test file.
| -rw-r--r-- | gas/testsuite/gas/aarch64/advsimd-fp16.d | 11 | ||||
| -rw-r--r-- | gas/testsuite/gas/aarch64/advsimd-fp16.s | 13 |
2 files changed, 22 insertions, 2 deletions
diff --git a/gas/testsuite/gas/aarch64/advsimd-fp16.d b/gas/testsuite/gas/aarch64/advsimd-fp16.d index 4efa9e8..ffac0d3 100644 --- a/gas/testsuite/gas/aarch64/advsimd-fp16.d +++ b/gas/testsuite/gas/aarch64/advsimd-fp16.d @@ -69,6 +69,13 @@ Disassembly of section \.text: *[0-9a-f]+: 0ec31441 fsub v1\.4h, v2\.4h, v3\.4h *[0-9a-f]+: 4ec01400 fsub v0\.8h, v0\.8h, v0\.8h *[0-9a-f]+: 4ec31441 fsub v1\.8h, v2\.8h, v3\.8h + *[0-9a-f]+: 6ee3d441 fabd v1.2d, v2.2d, v3.2d + *[0-9a-f]+: 2ea3d441 fabd v1.2s, v2.2s, v3.2s + *[0-9a-f]+: 6ea3d441 fabd v1.4s, v2.4s, v3.4s + *[0-9a-f]+: 2ec01400 fabd v0.4h, v0.4h, v0.4h + *[0-9a-f]+: 2ec31441 fabd v1.4h, v2.4h, v3.4h + *[0-9a-f]+: 6ec01400 fabd v0.8h, v0.8h, v0.8h + *[0-9a-f]+: 6ec31441 fabd v1.8h, v2.8h, v3.8h *[0-9a-f]+: 4e63dc41 fmulx v1\.2d, v2\.2d, v3\.2d *[0-9a-f]+: 0e23dc41 fmulx v1\.2s, v2\.2s, v3\.2s *[0-9a-f]+: 4e23dc41 fmulx v1\.4s, v2\.4s, v3\.4s @@ -323,6 +330,10 @@ Disassembly of section \.text: *[0-9a-f]+: 6e21c820 fcvtau v0\.4s, v1\.4s *[0-9a-f]+: 2e79c820 fcvtau v0\.4h, v1\.4h *[0-9a-f]+: 6e79c820 fcvtau v0\.8h, v1\.8h + *[0-9a-f]+: 0ea1c820 urecpe v0.2s, v1.2s + *[0-9a-f]+: 4ea1c820 urecpe v0.4s, v1.4s + *[0-9a-f]+: 2ea1c820 ursqrte v0.2s, v1.2s + *[0-9a-f]+: 6ea1c820 ursqrte v0.4s, v1.4s *[0-9a-f]+: 4e61d820 scvtf v0\.2d, v1\.2d *[0-9a-f]+: 0e21d820 scvtf v0\.2s, v1\.2s *[0-9a-f]+: 4e21d820 scvtf v0\.4s, v1\.4s diff --git a/gas/testsuite/gas/aarch64/advsimd-fp16.s b/gas/testsuite/gas/aarch64/advsimd-fp16.s index 6b86ded..2a09351 100644 --- a/gas/testsuite/gas/aarch64/advsimd-fp16.s +++ b/gas/testsuite/gas/aarch64/advsimd-fp16.s @@ -1,5 +1,6 @@ -/* simdhp.s Test file for AArch64 half-precision floating-point - vector instructions. */ +/* Test file for AArch64 half-precision floating-point vector instructions. + This is also the only test for the single- and double-precison variants of + most of these instructions. */ /* Vector three-same. */ @@ -24,6 +25,7 @@ three_same fadd three_same faddp three_same fsub + three_same fabd three_same fmulx three_same fmul three_same fcmeq @@ -82,6 +84,11 @@ \op v0.8h, v1.8h .endm + .macro tworeg_misc_s, op + \op v0.2s, v1.2s + \op v0.4s, v1.4s + .endm + tworeg_misc fabs tworeg_misc fneg @@ -106,6 +113,8 @@ tworeg_misc fcvtas tworeg_misc fcvtau + tworeg_misc_s urecpe + tworeg_misc_s ursqrte tworeg_misc scvtf tworeg_misc ucvtf |