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| author | Alice Carlotti <alice.carlotti@arm.com> | 2025-04-17 20:22:22 +0100 |
|---|---|---|
| committer | Alice Carlotti <alice.carlotti@arm.com> | 2025-05-09 20:27:22 +0100 |
| commit | a8d71f52d0729376ff1dfa27a60a07cc8d4dff40 (patch) | |
| tree | 3dba3e6109d19c1eaf28946ca29507742847d847 | |
| parent | db36339860e2752cacd80b734f350390551927ec (diff) | |
| download | binutils-a8d71f52d0729376ff1dfa27a60a07cc8d4dff40.zip binutils-a8d71f52d0729376ff1dfa27a60a07cc8d4dff40.tar.gz binutils-a8d71f52d0729376ff1dfa27a60a07cc8d4dff40.tar.bz2 | |
aarch64: Mark rev64 as a pseudo instruction
This is more natural than raising the priority of rev with F_P1, and
is functionally equivalent.
| -rw-r--r-- | opcodes/aarch64-asm-2.c | 2 | ||||
| -rw-r--r-- | opcodes/aarch64-dis-2.c | 4 | ||||
| -rw-r--r-- | opcodes/aarch64-tbl.h | 4 |
3 files changed, 5 insertions, 5 deletions
diff --git a/opcodes/aarch64-asm-2.c b/opcodes/aarch64-asm-2.c index 4e1f117..b4ce5f4 100644 --- a/opcodes/aarch64-asm-2.c +++ b/opcodes/aarch64-asm-2.c @@ -149,8 +149,8 @@ aarch64_find_real_opcode (const aarch64_opcode *opcode) case 669: /* csneg */ value = 669; /* --> csneg. */ break; - case 688: /* rev */ case 689: /* rev64 */ + case 688: /* rev */ value = 688; /* --> rev. */ break; case 714: /* lsl */ diff --git a/opcodes/aarch64-dis-2.c b/opcodes/aarch64-dis-2.c index 2e16794..84285ff 100644 --- a/opcodes/aarch64-dis-2.c +++ b/opcodes/aarch64-dis-2.c @@ -34914,7 +34914,7 @@ aarch64_find_alias_opcode (const aarch64_opcode *opcode) case 663: value = 665; break; /* csinc --> cset. */ case 666: value = 668; break; /* csinv --> csetm. */ case 669: value = 670; break; /* csneg --> cneg. */ - case 688: value = 688; break; /* rev --> rev. */ + case 688: value = 689; break; /* rev --> rev64. */ case 713: value = 714; break; /* lslv --> lsl. */ case 715: value = 716; break; /* lsrv --> lsr. */ case 717: value = 718; break; /* asrv --> asr. */ @@ -35074,7 +35074,7 @@ aarch64_find_next_alias_opcode (const aarch64_opcode *opcode) case 668: value = 667; break; /* csetm --> cinv. */ case 667: value = 666; break; /* cinv --> csinv. */ case 670: value = 669; break; /* cneg --> csneg. */ - case 688: value = 689; break; /* rev --> rev64. */ + case 689: value = 688; break; /* rev64 --> rev. */ case 714: value = 713; break; /* lsl --> lslv. */ case 716: value = 715; break; /* lsr --> lsrv. */ case 718: value = 717; break; /* asr --> asrv. */ diff --git a/opcodes/aarch64-tbl.h b/opcodes/aarch64-tbl.h index 7bfe128..70cf2e4 100644 --- a/opcodes/aarch64-tbl.h +++ b/opcodes/aarch64-tbl.h @@ -4002,8 +4002,8 @@ const struct aarch64_opcode aarch64_opcode_table[] = CORE_INSN ("rbit", 0x5ac00000, 0x7ffffc00, dp_1src, 0, OP2 (Rd, Rn), QL_I2SAME, F_SF), CORE_INSN ("rev16", 0x5ac00400, 0x7ffffc00, dp_1src, 0, OP2 (Rd, Rn), QL_I2SAME, F_SF), CORE_INSN ("rev", 0x5ac00800, 0xfffffc00, dp_1src, 0, OP2 (Rd, Rn), QL_I2SAMEW, 0), - CORE_INSN ("rev", 0xdac00c00, 0xfffffc00, dp_1src, 0, OP2 (Rd, Rn), QL_I2SAMEX, F_SF | F_HAS_ALIAS | F_P1), - CORE_INSN ("rev64", 0xdac00c00, 0xfffffc00, dp_1src, 0, OP2 (Rd, Rn), QL_I2SAMEX, F_SF | F_ALIAS), + CORE_INSN ("rev", 0xdac00c00, 0xfffffc00, dp_1src, 0, OP2 (Rd, Rn), QL_I2SAMEX, F_SF | F_HAS_ALIAS), + CORE_INSN ("rev64", 0xdac00c00, 0xfffffc00, dp_1src, 0, OP2 (Rd, Rn), QL_I2SAMEX, F_SF | F_ALIAS | F_PSEUDO), CORE_INSN ("clz", 0x5ac01000, 0x7ffffc00, dp_1src, 0, OP2 (Rd, Rn), QL_I2SAME, F_SF), CORE_INSN ("cls", 0x5ac01400, 0x7ffffc00, dp_1src, 0, OP2 (Rd, Rn), QL_I2SAME, F_SF), CORE_INSN ("rev32", 0xdac00800, 0xfffffc00, dp_1src, 0, OP2 (Rd, Rn), QL_I2SAMEX, 0), |