aarch64: Use operand class to select movprfx error

Previously the choice of error message for an invalid movprfx sequence
used the architecture requirements to determine whether an instruction
was an SVE instruction or not.  This meant specifying SVE or SVE2 as an
explicit architecture requirement for all SVE instructions, even when
this was already implied by another feature.  As more architecture
features are added and with the partial removal of the SME->SVE2
dependency, these extra feature requirements were getting messier and
easier to forget.

Instead, we now look at the operand types.  If there is an SVE_REG,
SVE_REGLIST or PRED_REG operand, then we treat the instruction as an SVE
instruction.  This does change behaviour slightly, but it only affects
the choice of error message and the new choice should be a bit more
consistent.

There is one testsuite update required, because Ezra's SVE_AES2 patch
temporarily broke classification of FEAT_SVE_AES instructions.  This
patch restores the original behaviour.

3 files changed, 20 insertions, 14 deletions

diff --git a/gas/testsuite/gas/aarch64/illegal-sve2.l b/gas/testsuite/gas/aarch64/illegal-sve2.l
index 62f063a..4b97425 100644
--- a/gas/testsuite/gas/aarch64/illegal-sve2.l
+++ b/gas/testsuite/gas/aarch64/illegal-sve2.l
@@ -50,27 +50,27 @@
 [^ :]+:[0-9]+: Error: expected a register at operand 1 -- `addp z32\.s,p0/m,z32\.s,z0\.s'
 [^ :]+:[0-9]+: Error: expected an SVE vector register at operand 4 -- `addp z0\.s,p0/m,z0\.s,z32\.s'
 [^ :]+:[0-9]+: Error: p0-p7 expected at operand 2 -- `addp z0\.s,p8/m,z0\.s,z0\.s'
-[^ :]+:[0-9]+: Warning: SVE instruction expected after `movprfx' -- `aesd z0\.b,z0\.b,z0\.b'
+[^ :]+:[0-9]+: Warning: SVE `movprfx' compatible instruction expected -- `aesd z0\.b,z0\.b,z0\.b'
 [^ :]+:[0-9]+: Error: operand 2 must be the same register as operand 1 -- `aesd z0\.b,z1\.b,z0\.b'
 [^ :]+:[0-9]+: Error: operand mismatch -- `aesd z0\.b,z0\.s,z0\.b'
 [^ :]+:[0-9]+: Info:    did you mean this\?
 [^ :]+:[0-9]+: Info:    	aesd z0\.b, z0\.b, z0\.b
 [^ :]+:[0-9]+: Error: expected a register or register list at operand 1 -- `aesd z32\.b,z0\.b,z0\.b'
 [^ :]+:[0-9]+: Error: expected an SVE vector register at operand 3 -- `aesd z0\.b,z0\.b,z32\.b'
-[^ :]+:[0-9]+: Warning: SVE instruction expected after `movprfx' -- `aese z0\.b,z0\.b,z0\.b'
+[^ :]+:[0-9]+: Warning: SVE `movprfx' compatible instruction expected -- `aese z0\.b,z0\.b,z0\.b'
 [^ :]+:[0-9]+: Error: operand 2 must be the same register as operand 1 -- `aese z0\.b,z1\.b,z0\.b'
 [^ :]+:[0-9]+: Error: operand mismatch -- `aese z0\.b,z0\.s,z0\.b'
 [^ :]+:[0-9]+: Info:    did you mean this\?
 [^ :]+:[0-9]+: Info:    	aese z0\.b, z0\.b, z0\.b
 [^ :]+:[0-9]+: Error: expected a register or register list at operand 1 -- `aese z32\.b,z0\.b,z0\.b'
 [^ :]+:[0-9]+: Error: expected an SVE vector register at operand 3 -- `aese z0\.b,z0\.b,z32\.b'
-[^ :]+:[0-9]+: Warning: SVE instruction expected after `movprfx' -- `aesimc z0\.b,z0\.b'
+[^ :]+:[0-9]+: Warning: SVE `movprfx' compatible instruction expected -- `aesimc z0\.b,z0\.b'
 [^ :]+:[0-9]+: Error: operand 2 must be the same register as operand 1 -- `aesimc z0\.b,z1\.b'
 [^ :]+:[0-9]+: Error: operand mismatch -- `aesimc z0\.b,z0\.s'
 [^ :]+:[0-9]+: Info:    did you mean this\?
 [^ :]+:[0-9]+: Info:    	aesimc z0\.b, z0\.b
 [^ :]+:[0-9]+: Error: expected a vector register at operand 1 -- `aesimc z32\.b,z0\.b'
-[^ :]+:[0-9]+: Warning: SVE instruction expected after `movprfx' -- `aesmc z0\.b,z0\.b'
+[^ :]+:[0-9]+: Warning: SVE `movprfx' compatible instruction expected -- `aesmc z0\.b,z0\.b'
 [^ :]+:[0-9]+: Error: operand 2 must be the same register as operand 1 -- `aesmc z0\.b,z1\.b'
 [^ :]+:[0-9]+: Error: operand mismatch -- `aesmc z0\.b,z0\.s'
 [^ :]+:[0-9]+: Info:    did you mean this\?
diff --git a/opcodes/aarch64-opc.c b/opcodes/aarch64-opc.c
index 4de7965..9c4e181 100644
--- a/opcodes/aarch64-opc.c
+++ b/opcodes/aarch64-opc.c
@@ -5720,10 +5720,21 @@ verify_constraints (const struct aarch64_inst *inst,
 	{
 	  /* Check to see if the MOVPRFX SVE instruction is followed by an SVE
 	     instruction for better error messages.  */
-	  if (!opcode->avariant
-	      || (!AARCH64_CPU_HAS_FEATURE (*opcode->avariant, SVE)
-		  && !AARCH64_CPU_HAS_FEATURE (*opcode->avariant, SVE2)
-		  && !AARCH64_CPU_HAS_FEATURE (*opcode->avariant, SVE2p1)))
+	  bool sve_operand_p = false;
+	  for (int i = 0; i < AARCH64_MAX_OPND_NUM; ++i)
+	    {
+	      enum aarch64_operand_class op_class
+		= aarch64_get_operand_class (opcode->operands[i]);
+	      if (op_class == AARCH64_OPND_CLASS_SVE_REG
+		  || op_class == AARCH64_OPND_CLASS_SVE_REGLIST
+		  || op_class == AARCH64_OPND_CLASS_PRED_REG)
+		{
+		  sve_operand_p = true;
+		  break;
+		}
+	    }
+
+	  if (!sve_operand_p)
 	    {
 	      mismatch_detail->kind = AARCH64_OPDE_SYNTAX_ERROR;
 	      mismatch_detail->error = _("SVE instruction expected after "
diff --git a/opcodes/aarch64-tbl.h b/opcodes/aarch64-tbl.h
index 05a5e6f..4116f0c 100644
--- a/opcodes/aarch64-tbl.h
+++ b/opcodes/aarch64-tbl.h
@@ -2789,12 +2789,7 @@
   QLF3(V_4S, V_8H, S_H),	\
 }
 
-/* Opcode table.
-
-  Any SVE or SVE2 feature must include AARCH64_FEATURE_{SVE|SVE2} in its
-  bitmask, even if this is implied by other selected feature bits.  This
-  allows verify_constraints to identify SVE instructions when selecting an
-  error message for MOVPRFX constraint violations.  */
+/* Opcode table.  */
 
 static const aarch64_feature_set aarch64_feature_v8 =
   AARCH64_FEATURE (V8);