sim: ft32: move libsim.a creation to top-level

The objects are still compiled in the subdir, but the creation of the
archive itself is in the top-level.  This is a required step before we
can move compilation itself up, and makes it easier to review.

The downside is that each object compile is a recursive make instead of
a single one.  On my 4 core system, it adds ~100msec to the build per
port, so it's not great, but it shouldn't be a big deal.  This will go
away of course once the top-level compiles objects.

3 files changed, 133 insertions, 86 deletions

diff --git a/sim/Makefile.in b/sim/Makefile.in
index 4d3022f..a6216c3 100644
--- a/sim/Makefile.in
+++ b/sim/Makefile.in
@@ -191,66 +191,67 @@ TESTS = testsuite/common/bits32m0$(EXEEXT) \
 @SIM_ENABLE_ARCH_frv_TRUE@am__append_49 = frv/eng.h
 @SIM_ENABLE_ARCH_frv_TRUE@am__append_50 = $(frv_BUILD_OUTPUTS)
 @SIM_ENABLE_ARCH_frv_TRUE@am__append_51 = $(frv_BUILD_OUTPUTS)
-@SIM_ENABLE_ARCH_ft32_TRUE@am__append_52 = ft32/run
-@SIM_ENABLE_ARCH_h8300_TRUE@am__append_53 = h8300/run
-@SIM_ENABLE_ARCH_iq2000_TRUE@am__append_54 = iq2000/run
-@SIM_ENABLE_ARCH_iq2000_TRUE@am__append_55 = iq2000/eng.h
-@SIM_ENABLE_ARCH_iq2000_TRUE@am__append_56 = $(iq2000_BUILD_OUTPUTS)
+@SIM_ENABLE_ARCH_ft32_TRUE@am__append_52 = ft32/libsim.a
+@SIM_ENABLE_ARCH_ft32_TRUE@am__append_53 = ft32/run
+@SIM_ENABLE_ARCH_h8300_TRUE@am__append_54 = h8300/run
+@SIM_ENABLE_ARCH_iq2000_TRUE@am__append_55 = iq2000/run
+@SIM_ENABLE_ARCH_iq2000_TRUE@am__append_56 = iq2000/eng.h
 @SIM_ENABLE_ARCH_iq2000_TRUE@am__append_57 = $(iq2000_BUILD_OUTPUTS)
-@SIM_ENABLE_ARCH_lm32_TRUE@am__append_58 = lm32/run
-@SIM_ENABLE_ARCH_lm32_TRUE@am__append_59 = lm32_SIM_EXTRA_HW_DEVICES="$(lm32_SIM_EXTRA_HW_DEVICES)"
-@SIM_ENABLE_ARCH_lm32_TRUE@am__append_60 = lm32/eng.h
-@SIM_ENABLE_ARCH_lm32_TRUE@am__append_61 = $(lm32_BUILD_OUTPUTS)
+@SIM_ENABLE_ARCH_iq2000_TRUE@am__append_58 = $(iq2000_BUILD_OUTPUTS)
+@SIM_ENABLE_ARCH_lm32_TRUE@am__append_59 = lm32/run
+@SIM_ENABLE_ARCH_lm32_TRUE@am__append_60 = lm32_SIM_EXTRA_HW_DEVICES="$(lm32_SIM_EXTRA_HW_DEVICES)"
+@SIM_ENABLE_ARCH_lm32_TRUE@am__append_61 = lm32/eng.h
 @SIM_ENABLE_ARCH_lm32_TRUE@am__append_62 = $(lm32_BUILD_OUTPUTS)
-@SIM_ENABLE_ARCH_m32c_TRUE@am__append_63 = m32c/run
-@SIM_ENABLE_ARCH_m32c_TRUE@am__append_64 = $(m32c_BUILD_OUTPUTS)
-@SIM_ENABLE_ARCH_m32c_TRUE@am__append_65 = m32c/opc2c
-@SIM_ENABLE_ARCH_m32c_TRUE@am__append_66 = \
+@SIM_ENABLE_ARCH_lm32_TRUE@am__append_63 = $(lm32_BUILD_OUTPUTS)
+@SIM_ENABLE_ARCH_m32c_TRUE@am__append_64 = m32c/run
+@SIM_ENABLE_ARCH_m32c_TRUE@am__append_65 = $(m32c_BUILD_OUTPUTS)
+@SIM_ENABLE_ARCH_m32c_TRUE@am__append_66 = m32c/opc2c
+@SIM_ENABLE_ARCH_m32c_TRUE@am__append_67 = \
 @SIM_ENABLE_ARCH_m32c_TRUE@	$(m32c_BUILD_OUTPUTS) \
 @SIM_ENABLE_ARCH_m32c_TRUE@	m32c/m32c.c.log \
 @SIM_ENABLE_ARCH_m32c_TRUE@	m32c/r8c.c.log
 
-@SIM_ENABLE_ARCH_m32r_TRUE@am__append_67 = m32r/run
-@SIM_ENABLE_ARCH_m32r_TRUE@am__append_68 = m32r_SIM_EXTRA_HW_DEVICES="$(m32r_SIM_EXTRA_HW_DEVICES)"
-@SIM_ENABLE_ARCH_m32r_TRUE@am__append_69 = \
+@SIM_ENABLE_ARCH_m32r_TRUE@am__append_68 = m32r/run
+@SIM_ENABLE_ARCH_m32r_TRUE@am__append_69 = m32r_SIM_EXTRA_HW_DEVICES="$(m32r_SIM_EXTRA_HW_DEVICES)"
+@SIM_ENABLE_ARCH_m32r_TRUE@am__append_70 = \
 @SIM_ENABLE_ARCH_m32r_TRUE@	m32r/eng.h \
 @SIM_ENABLE_ARCH_m32r_TRUE@	m32r/engx.h \
 @SIM_ENABLE_ARCH_m32r_TRUE@	m32r/eng2.h
 
-@SIM_ENABLE_ARCH_m32r_TRUE@am__append_70 = $(m32r_BUILD_OUTPUTS)
 @SIM_ENABLE_ARCH_m32r_TRUE@am__append_71 = $(m32r_BUILD_OUTPUTS)
-@SIM_ENABLE_ARCH_m68hc11_TRUE@am__append_72 = m68hc11/run
-@SIM_ENABLE_ARCH_m68hc11_TRUE@am__append_73 = m68hc11_SIM_EXTRA_HW_DEVICES="$(m68hc11_SIM_EXTRA_HW_DEVICES)"
-@SIM_ENABLE_ARCH_m68hc11_TRUE@am__append_74 = $(m68hc11_BUILD_OUTPUTS)
-@SIM_ENABLE_ARCH_m68hc11_TRUE@am__append_75 = m68hc11/gencode
-@SIM_ENABLE_ARCH_m68hc11_TRUE@am__append_76 = $(m68hc11_BUILD_OUTPUTS)
-@SIM_ENABLE_ARCH_mcore_TRUE@am__append_77 = mcore/run
-@SIM_ENABLE_ARCH_microblaze_TRUE@am__append_78 = microblaze/run
-@SIM_ENABLE_ARCH_mips_TRUE@am__append_79 = mips/run
-@SIM_ENABLE_ARCH_mips_TRUE@am__append_80 = mips_SIM_EXTRA_HW_DEVICES="$(mips_SIM_EXTRA_HW_DEVICES)"
-@SIM_ENABLE_ARCH_mips_TRUE@am__append_81 = mips/itable.h \
+@SIM_ENABLE_ARCH_m32r_TRUE@am__append_72 = $(m32r_BUILD_OUTPUTS)
+@SIM_ENABLE_ARCH_m68hc11_TRUE@am__append_73 = m68hc11/run
+@SIM_ENABLE_ARCH_m68hc11_TRUE@am__append_74 = m68hc11_SIM_EXTRA_HW_DEVICES="$(m68hc11_SIM_EXTRA_HW_DEVICES)"
+@SIM_ENABLE_ARCH_m68hc11_TRUE@am__append_75 = $(m68hc11_BUILD_OUTPUTS)
+@SIM_ENABLE_ARCH_m68hc11_TRUE@am__append_76 = m68hc11/gencode
+@SIM_ENABLE_ARCH_m68hc11_TRUE@am__append_77 = $(m68hc11_BUILD_OUTPUTS)
+@SIM_ENABLE_ARCH_mcore_TRUE@am__append_78 = mcore/run
+@SIM_ENABLE_ARCH_microblaze_TRUE@am__append_79 = microblaze/run
+@SIM_ENABLE_ARCH_mips_TRUE@am__append_80 = mips/run
+@SIM_ENABLE_ARCH_mips_TRUE@am__append_81 = mips_SIM_EXTRA_HW_DEVICES="$(mips_SIM_EXTRA_HW_DEVICES)"
+@SIM_ENABLE_ARCH_mips_TRUE@am__append_82 = mips/itable.h \
 @SIM_ENABLE_ARCH_mips_TRUE@	$(SIM_MIPS_MULTI_SRC)
-@SIM_ENABLE_ARCH_mips_TRUE@@SIM_MIPS_GEN_MODE_SINGLE_TRUE@am__append_82 = \
+@SIM_ENABLE_ARCH_mips_TRUE@@SIM_MIPS_GEN_MODE_SINGLE_TRUE@am__append_83 = \
 @SIM_ENABLE_ARCH_mips_TRUE@@SIM_MIPS_GEN_MODE_SINGLE_TRUE@	$(mips_BUILT_SRC_FROM_GEN_MODE_SINGLE) \
 @SIM_ENABLE_ARCH_mips_TRUE@@SIM_MIPS_GEN_MODE_SINGLE_TRUE@	mips/stamp-gen-mode-single
 
-@SIM_ENABLE_ARCH_mips_TRUE@@SIM_MIPS_GEN_MODE_M16_TRUE@am__append_83 = \
+@SIM_ENABLE_ARCH_mips_TRUE@@SIM_MIPS_GEN_MODE_M16_TRUE@am__append_84 = \
 @SIM_ENABLE_ARCH_mips_TRUE@@SIM_MIPS_GEN_MODE_M16_TRUE@	$(mips_BUILT_SRC_FROM_GEN_MODE_M16_M16) \
 @SIM_ENABLE_ARCH_mips_TRUE@@SIM_MIPS_GEN_MODE_M16_TRUE@	$(mips_BUILT_SRC_FROM_GEN_MODE_M16_M32) \
 @SIM_ENABLE_ARCH_mips_TRUE@@SIM_MIPS_GEN_MODE_M16_TRUE@	mips/stamp-gen-mode-m16-m16 \
 @SIM_ENABLE_ARCH_mips_TRUE@@SIM_MIPS_GEN_MODE_M16_TRUE@	mips/stamp-gen-mode-m16-m32
 
-@SIM_ENABLE_ARCH_mips_TRUE@@SIM_MIPS_GEN_MODE_MULTI_TRUE@am__append_84 = \
+@SIM_ENABLE_ARCH_mips_TRUE@@SIM_MIPS_GEN_MODE_MULTI_TRUE@am__append_85 = \
 @SIM_ENABLE_ARCH_mips_TRUE@@SIM_MIPS_GEN_MODE_MULTI_TRUE@	$(SIM_MIPS_MULTI_SRC) \
 @SIM_ENABLE_ARCH_mips_TRUE@@SIM_MIPS_GEN_MODE_MULTI_TRUE@	mips/stamp-gen-mode-multi-igen \
 @SIM_ENABLE_ARCH_mips_TRUE@@SIM_MIPS_GEN_MODE_MULTI_TRUE@	mips/stamp-gen-mode-multi-run
 
-@SIM_ENABLE_ARCH_mips_TRUE@am__append_85 = $(mips_BUILD_OUTPUTS)
 @SIM_ENABLE_ARCH_mips_TRUE@am__append_86 = $(mips_BUILD_OUTPUTS)
-@SIM_ENABLE_ARCH_mips_TRUE@am__append_87 = mips/multi-include.h mips/multi-run.c
-@SIM_ENABLE_ARCH_mn10300_TRUE@am__append_88 = mn10300/run
-@SIM_ENABLE_ARCH_mn10300_TRUE@am__append_89 = mn10300_SIM_EXTRA_HW_DEVICES="$(mn10300_SIM_EXTRA_HW_DEVICES)"
-@SIM_ENABLE_ARCH_mn10300_TRUE@am__append_90 = \
+@SIM_ENABLE_ARCH_mips_TRUE@am__append_87 = $(mips_BUILD_OUTPUTS)
+@SIM_ENABLE_ARCH_mips_TRUE@am__append_88 = mips/multi-include.h mips/multi-run.c
+@SIM_ENABLE_ARCH_mn10300_TRUE@am__append_89 = mn10300/run
+@SIM_ENABLE_ARCH_mn10300_TRUE@am__append_90 = mn10300_SIM_EXTRA_HW_DEVICES="$(mn10300_SIM_EXTRA_HW_DEVICES)"
+@SIM_ENABLE_ARCH_mn10300_TRUE@am__append_91 = \
 @SIM_ENABLE_ARCH_mn10300_TRUE@	mn10300/icache.h \
 @SIM_ENABLE_ARCH_mn10300_TRUE@	mn10300/idecode.h \
 @SIM_ENABLE_ARCH_mn10300_TRUE@	mn10300/semantics.h \
@@ -259,29 +260,29 @@ TESTS = testsuite/common/bits32m0$(EXEEXT) \
 @SIM_ENABLE_ARCH_mn10300_TRUE@	mn10300/itable.h \
 @SIM_ENABLE_ARCH_mn10300_TRUE@	mn10300/engine.h
 
-@SIM_ENABLE_ARCH_mn10300_TRUE@am__append_91 = $(mn10300_BUILD_OUTPUTS)
 @SIM_ENABLE_ARCH_mn10300_TRUE@am__append_92 = $(mn10300_BUILD_OUTPUTS)
-@SIM_ENABLE_ARCH_moxie_TRUE@am__append_93 = moxie/run
-@SIM_ENABLE_ARCH_msp430_TRUE@am__append_94 = msp430/run
-@SIM_ENABLE_ARCH_or1k_TRUE@am__append_95 = or1k/run
-@SIM_ENABLE_ARCH_or1k_TRUE@am__append_96 = or1k/eng.h
-@SIM_ENABLE_ARCH_or1k_TRUE@am__append_97 = $(or1k_BUILD_OUTPUTS)
+@SIM_ENABLE_ARCH_mn10300_TRUE@am__append_93 = $(mn10300_BUILD_OUTPUTS)
+@SIM_ENABLE_ARCH_moxie_TRUE@am__append_94 = moxie/run
+@SIM_ENABLE_ARCH_msp430_TRUE@am__append_95 = msp430/run
+@SIM_ENABLE_ARCH_or1k_TRUE@am__append_96 = or1k/run
+@SIM_ENABLE_ARCH_or1k_TRUE@am__append_97 = or1k/eng.h
 @SIM_ENABLE_ARCH_or1k_TRUE@am__append_98 = $(or1k_BUILD_OUTPUTS)
-@SIM_ENABLE_ARCH_ppc_TRUE@am__append_99 = ppc/run ppc/psim
-@SIM_ENABLE_ARCH_pru_TRUE@am__append_100 = pru/run
-@SIM_ENABLE_ARCH_riscv_TRUE@am__append_101 = riscv/run
-@SIM_ENABLE_ARCH_rl78_TRUE@am__append_102 = rl78/run
-@SIM_ENABLE_ARCH_rx_TRUE@am__append_103 = rx/run
-@SIM_ENABLE_ARCH_sh_TRUE@am__append_104 = sh/run
-@SIM_ENABLE_ARCH_sh_TRUE@am__append_105 = \
+@SIM_ENABLE_ARCH_or1k_TRUE@am__append_99 = $(or1k_BUILD_OUTPUTS)
+@SIM_ENABLE_ARCH_ppc_TRUE@am__append_100 = ppc/run ppc/psim
+@SIM_ENABLE_ARCH_pru_TRUE@am__append_101 = pru/run
+@SIM_ENABLE_ARCH_riscv_TRUE@am__append_102 = riscv/run
+@SIM_ENABLE_ARCH_rl78_TRUE@am__append_103 = rl78/run
+@SIM_ENABLE_ARCH_rx_TRUE@am__append_104 = rx/run
+@SIM_ENABLE_ARCH_sh_TRUE@am__append_105 = sh/run
+@SIM_ENABLE_ARCH_sh_TRUE@am__append_106 = \
 @SIM_ENABLE_ARCH_sh_TRUE@	sh/code.c \
 @SIM_ENABLE_ARCH_sh_TRUE@	sh/ppi.c
 
-@SIM_ENABLE_ARCH_sh_TRUE@am__append_106 = $(sh_BUILD_OUTPUTS)
-@SIM_ENABLE_ARCH_sh_TRUE@am__append_107 = sh/gencode
-@SIM_ENABLE_ARCH_sh_TRUE@am__append_108 = $(sh_BUILD_OUTPUTS)
-@SIM_ENABLE_ARCH_v850_TRUE@am__append_109 = v850/run
-@SIM_ENABLE_ARCH_v850_TRUE@am__append_110 = \
+@SIM_ENABLE_ARCH_sh_TRUE@am__append_107 = $(sh_BUILD_OUTPUTS)
+@SIM_ENABLE_ARCH_sh_TRUE@am__append_108 = sh/gencode
+@SIM_ENABLE_ARCH_sh_TRUE@am__append_109 = $(sh_BUILD_OUTPUTS)
+@SIM_ENABLE_ARCH_v850_TRUE@am__append_110 = v850/run
+@SIM_ENABLE_ARCH_v850_TRUE@am__append_111 = \
 @SIM_ENABLE_ARCH_v850_TRUE@	v850/icache.h \
 @SIM_ENABLE_ARCH_v850_TRUE@	v850/idecode.h \
 @SIM_ENABLE_ARCH_v850_TRUE@	v850/semantics.h \
@@ -290,8 +291,8 @@ TESTS = testsuite/common/bits32m0$(EXEEXT) \
 @SIM_ENABLE_ARCH_v850_TRUE@	v850/itable.h \
 @SIM_ENABLE_ARCH_v850_TRUE@	v850/engine.h
 
-@SIM_ENABLE_ARCH_v850_TRUE@am__append_111 = $(v850_BUILD_OUTPUTS)
 @SIM_ENABLE_ARCH_v850_TRUE@am__append_112 = $(v850_BUILD_OUTPUTS)
+@SIM_ENABLE_ARCH_v850_TRUE@am__append_113 = $(v850_BUILD_OUTPUTS)
 subdir = .
 ACLOCAL_M4 = $(top_srcdir)/aclocal.m4
 am__aclocal_m4_deps = $(top_srcdir)/../config/acx.m4 \
@@ -525,6 +526,17 @@ frv_libsim_a_AR = $(AR) $(ARFLAGS)
 @SIM_ENABLE_ARCH_frv_TRUE@	frv/reset.o frv/sim-if.o frv/traps.o
 am_frv_libsim_a_OBJECTS =
 frv_libsim_a_OBJECTS = $(am_frv_libsim_a_OBJECTS)
+ft32_libsim_a_AR = $(AR) $(ARFLAGS)
+@SIM_ENABLE_ARCH_ft32_TRUE@ft32_libsim_a_DEPENDENCIES =  \
+@SIM_ENABLE_ARCH_ft32_TRUE@	$(common_libcommon_a_OBJECTS) \
+@SIM_ENABLE_ARCH_ft32_TRUE@	$(patsubst \
+@SIM_ENABLE_ARCH_ft32_TRUE@	%,ft32/%,$(SIM_NEW_COMMON_OBJS)) \
+@SIM_ENABLE_ARCH_ft32_TRUE@	$(patsubst \
+@SIM_ENABLE_ARCH_ft32_TRUE@	%,ft32/dv-%.o,$(SIM_HW_DEVICES)) \
+@SIM_ENABLE_ARCH_ft32_TRUE@	ft32/interp.o ft32/modules.o \
+@SIM_ENABLE_ARCH_ft32_TRUE@	ft32/sim-resume.o
+am_ft32_libsim_a_OBJECTS =
+ft32_libsim_a_OBJECTS = $(am_ft32_libsim_a_OBJECTS)
 igen_libigen_a_AR = $(AR) $(ARFLAGS)
 igen_libigen_a_LIBADD =
 @SIM_ENABLE_IGEN_TRUE@am_igen_libigen_a_OBJECTS =  \
@@ -873,12 +885,12 @@ SOURCES = $(aarch64_libsim_a_SOURCES) $(arm_libsim_a_SOURCES) \
 	$(cr16_libsim_a_SOURCES) $(cris_libsim_a_SOURCES) \
 	$(d10v_libsim_a_SOURCES) $(erc32_libsim_a_SOURCES) \
 	$(example_synacor_libsim_a_SOURCES) $(frv_libsim_a_SOURCES) \
-	$(igen_libigen_a_SOURCES) $(aarch64_run_SOURCES) \
-	$(arm_run_SOURCES) $(avr_run_SOURCES) $(bfin_run_SOURCES) \
-	$(bpf_run_SOURCES) $(cr16_gencode_SOURCES) $(cr16_run_SOURCES) \
-	$(cris_run_SOURCES) $(cris_rvdummy_SOURCES) \
-	$(d10v_gencode_SOURCES) $(d10v_run_SOURCES) \
-	$(erc32_run_SOURCES) erc32/sis.c \
+	$(ft32_libsim_a_SOURCES) $(igen_libigen_a_SOURCES) \
+	$(aarch64_run_SOURCES) $(arm_run_SOURCES) $(avr_run_SOURCES) \
+	$(bfin_run_SOURCES) $(bpf_run_SOURCES) $(cr16_gencode_SOURCES) \
+	$(cr16_run_SOURCES) $(cris_run_SOURCES) \
+	$(cris_rvdummy_SOURCES) $(d10v_gencode_SOURCES) \
+	$(d10v_run_SOURCES) $(erc32_run_SOURCES) erc32/sis.c \
 	$(example_synacor_run_SOURCES) $(frv_run_SOURCES) \
 	$(ft32_run_SOURCES) $(h8300_run_SOURCES) \
 	$(igen_filter_SOURCES) $(igen_gen_SOURCES) \
@@ -1430,34 +1442,34 @@ srcroot = $(srcdir)/..
 SUBDIRS = @subdirs@ $(SIM_SUBDIRS)
 AM_MAKEFLAGS = SIM_NEW_COMMON_OBJS_="$(SIM_NEW_COMMON_OBJS)" \
 	$(am__append_3) $(am__append_16) $(am__append_30) \
-	$(am__append_59) $(am__append_68) $(am__append_73) \
-	$(am__append_80) $(am__append_89)
+	$(am__append_60) $(am__append_69) $(am__append_74) \
+	$(am__append_81) $(am__append_90)
 pkginclude_HEADERS = $(am__append_1)
 noinst_LIBRARIES = common/libcommon.a $(am__append_5) $(am__append_8) \
 	$(am__append_10) $(am__append_12) $(am__append_14) \
 	$(am__append_17) $(am__append_22) $(am__append_28) \
 	$(am__append_35) $(am__append_41) $(am__append_45) \
-	$(am__append_47)
+	$(am__append_47) $(am__append_52)
 BUILT_SOURCES = $(am__append_19) $(am__append_24) $(am__append_32) \
-	$(am__append_37) $(am__append_49) $(am__append_55) \
-	$(am__append_60) $(am__append_69) $(am__append_81) \
-	$(am__append_90) $(am__append_96) $(am__append_105) \
-	$(am__append_110)
+	$(am__append_37) $(am__append_49) $(am__append_56) \
+	$(am__append_61) $(am__append_70) $(am__append_82) \
+	$(am__append_91) $(am__append_97) $(am__append_106) \
+	$(am__append_111)
 CLEANFILES = common/version.c common/version.c-stamp \
 	testsuite/common/bits-gen testsuite/common/bits32m0.c \
 	testsuite/common/bits32m31.c testsuite/common/bits64m0.c \
 	testsuite/common/bits64m63.c
-DISTCLEANFILES = $(am__append_87)
+DISTCLEANFILES = $(am__append_88)
 MOSTLYCLEANFILES = core $(common_HW_CONFIG_H_TARGETS) $(patsubst \
 	%,%/stamp-hw,$(SIM_ENABLED_ARCHES)) \
 	$(common_GEN_MODULES_C_TARGETS) $(patsubst \
 	%,%/stamp-modules,$(SIM_ENABLED_ARCHES)) $(am__append_7) \
 	site-sim-config.exp testrun.log testrun.sum $(am__append_21) \
 	$(am__append_27) $(am__append_34) $(am__append_40) \
-	$(am__append_51) $(am__append_57) $(am__append_62) \
-	$(am__append_66) $(am__append_71) $(am__append_76) \
-	$(am__append_86) $(am__append_92) $(am__append_98) \
-	$(am__append_108) $(am__append_112)
+	$(am__append_51) $(am__append_58) $(am__append_63) \
+	$(am__append_67) $(am__append_72) $(am__append_77) \
+	$(am__append_87) $(am__append_93) $(am__append_99) \
+	$(am__append_109) $(am__append_113)
 AM_CFLAGS = $(WERROR_CFLAGS) $(WARN_CFLAGS)
 AM_CPPFLAGS = $(INCGNU) -I$(srcroot)/include -I../bfd -I.. \
 	$(SIM_HW_CFLAGS) $(SIM_INLINE) -I$(srcdir)/common \
@@ -1470,10 +1482,10 @@ SIM_ALL_RECURSIVE_DEPS = common/libcommon.a \
 	$(common_HW_CONFIG_H_TARGETS) $(common_GEN_MODULES_C_TARGETS) \
 	$(am__append_4) $(am__append_20) $(am__append_25) \
 	$(am__append_33) $(am__append_38) $(am__append_50) \
-	$(am__append_56) $(am__append_61) $(am__append_64) \
-	$(am__append_70) $(am__append_74) $(am__append_85) \
-	$(am__append_91) $(am__append_97) $(am__append_106) \
-	$(am__append_111)
+	$(am__append_57) $(am__append_62) $(am__append_65) \
+	$(am__append_71) $(am__append_75) $(am__append_86) \
+	$(am__append_92) $(am__append_98) $(am__append_107) \
+	$(am__append_112)
 SIM_INSTALL_DATA_LOCAL_DEPS = 
 SIM_INSTALL_EXEC_LOCAL_DEPS = $(am__append_43)
 SIM_UNINSTALL_LOCAL_DEPS = $(am__append_44)
@@ -1962,6 +1974,15 @@ testsuite_common_CPPFLAGS = \
 @SIM_ENABLE_ARCH_frv_TRUE@	frv/mloop.c \
 @SIM_ENABLE_ARCH_frv_TRUE@	frv/stamp-mloop
 
+@SIM_ENABLE_ARCH_ft32_TRUE@ft32_libsim_a_SOURCES = 
+@SIM_ENABLE_ARCH_ft32_TRUE@ft32_libsim_a_LIBADD = \
+@SIM_ENABLE_ARCH_ft32_TRUE@	$(common_libcommon_a_OBJECTS) \
+@SIM_ENABLE_ARCH_ft32_TRUE@	$(patsubst %,ft32/%,$(SIM_NEW_COMMON_OBJS)) \
+@SIM_ENABLE_ARCH_ft32_TRUE@	$(patsubst %,ft32/dv-%.o,$(SIM_HW_DEVICES)) \
+@SIM_ENABLE_ARCH_ft32_TRUE@	ft32/interp.o \
+@SIM_ENABLE_ARCH_ft32_TRUE@	ft32/modules.o \
+@SIM_ENABLE_ARCH_ft32_TRUE@	ft32/sim-resume.o
+
 @SIM_ENABLE_ARCH_ft32_TRUE@ft32_run_SOURCES = 
 @SIM_ENABLE_ARCH_ft32_TRUE@ft32_run_LDADD = \
 @SIM_ENABLE_ARCH_ft32_TRUE@	ft32/nrun.o \
@@ -2103,8 +2124,8 @@ testsuite_common_CPPFLAGS = \
 @SIM_ENABLE_ARCH_mips_TRUE@mips_BUILD_OUTPUTS =  \
 @SIM_ENABLE_ARCH_mips_TRUE@	$(mips_BUILT_SRC_FROM_IGEN_ITABLE) \
 @SIM_ENABLE_ARCH_mips_TRUE@	mips/stamp-igen-itable \
-@SIM_ENABLE_ARCH_mips_TRUE@	$(am__append_82) $(am__append_83) \
-@SIM_ENABLE_ARCH_mips_TRUE@	$(am__append_84)
+@SIM_ENABLE_ARCH_mips_TRUE@	$(am__append_83) $(am__append_84) \
+@SIM_ENABLE_ARCH_mips_TRUE@	$(am__append_85)
 @SIM_ENABLE_ARCH_mips_TRUE@mips_IGEN_TRACE = # -G omit-line-numbers # -G trace-rule-selection -G trace-rule-rejection -G trace-entries # -G trace-all
 @SIM_ENABLE_ARCH_mips_TRUE@mips_IGEN_INSN = $(srcdir)/mips/mips.igen
 @SIM_ENABLE_ARCH_mips_TRUE@mips_IGEN_INSN_INC = \
@@ -2565,6 +2586,14 @@ frv/libsim.a: $(frv_libsim_a_OBJECTS) $(frv_libsim_a_DEPENDENCIES) $(EXTRA_frv_l
 	$(AM_V_at)-rm -f frv/libsim.a
 	$(AM_V_AR)$(frv_libsim_a_AR) frv/libsim.a $(frv_libsim_a_OBJECTS) $(frv_libsim_a_LIBADD)
 	$(AM_V_at)$(RANLIB) frv/libsim.a
+ft32/$(am__dirstamp):
+	@$(MKDIR_P) ft32
+	@: > ft32/$(am__dirstamp)
+
+ft32/libsim.a: $(ft32_libsim_a_OBJECTS) $(ft32_libsim_a_DEPENDENCIES) $(EXTRA_ft32_libsim_a_DEPENDENCIES) ft32/$(am__dirstamp)
+	$(AM_V_at)-rm -f ft32/libsim.a
+	$(AM_V_AR)$(ft32_libsim_a_AR) ft32/libsim.a $(ft32_libsim_a_OBJECTS) $(ft32_libsim_a_LIBADD)
+	$(AM_V_at)$(RANLIB) ft32/libsim.a
 igen/$(am__dirstamp):
 	@$(MKDIR_P) igen
 	@: > igen/$(am__dirstamp)
@@ -2705,9 +2734,6 @@ example-synacor/run$(EXEEXT): $(example_synacor_run_OBJECTS) $(example_synacor_r
 frv/run$(EXEEXT): $(frv_run_OBJECTS) $(frv_run_DEPENDENCIES) $(EXTRA_frv_run_DEPENDENCIES) frv/$(am__dirstamp)
 	@rm -f frv/run$(EXEEXT)
 	$(AM_V_CCLD)$(LINK) $(frv_run_OBJECTS) $(frv_run_LDADD) $(LIBS)
-ft32/$(am__dirstamp):
-	@$(MKDIR_P) ft32
-	@: > ft32/$(am__dirstamp)
 
 ft32/run$(EXEEXT): $(ft32_run_OBJECTS) $(ft32_run_DEPENDENCIES) $(EXTRA_ft32_run_DEPENDENCIES) ft32/$(am__dirstamp)
 	@rm -f ft32/run$(EXEEXT)
@@ -4156,6 +4182,13 @@ testsuite/common/bits64m63.c: testsuite/common/bits-gen$(EXEEXT) testsuite/commo
 @SIM_ENABLE_ARCH_frv_TRUE@frv/cgen-cpu-decode:
 @SIM_ENABLE_ARCH_frv_TRUE@	$(AM_V_GEN)cpu=frvbf mach=frv,fr550,fr500,fr450,fr400,tomcat,simple FLAGS="with-scache with-profile=fn with-generic-write with-parallel-only" EXTRAFILES="$(CGEN_CPU_SEM)"; $(CGEN_GEN_CPU_DECODE)
 @SIM_ENABLE_ARCH_frv_TRUE@frv/cpu.h frv/sem.c frv/model.c frv/decode.c frv/decode.h: @CGEN_MAINT@ frv/cgen-cpu-decode
+@SIM_ENABLE_ARCH_ft32_TRUE@$(ft32_libsim_a_OBJECTS) $(ft32_libsim_a_LIBADD): ft32/hw-config.h
+
+@SIM_ENABLE_ARCH_ft32_TRUE@ft32/%.o: ft32/%.c
+@SIM_ENABLE_ARCH_ft32_TRUE@	$(AM_V_at)$(MAKE) $(AM_MAKEFLAGS) -C $(@D) $(@F)
+
+@SIM_ENABLE_ARCH_ft32_TRUE@ft32/%.o: common/%.c
+@SIM_ENABLE_ARCH_ft32_TRUE@	$(AM_V_at)$(MAKE) $(AM_MAKEFLAGS) -C $(@D) $(@F)
 @SIM_ENABLE_ARCH_iq2000_TRUE@iq2000/modules.c: | $(iq2000_BUILD_OUTPUTS)
 
 @SIM_ENABLE_ARCH_iq2000_TRUE@iq2000/mloop.c iq2000/eng.h: iq2000/stamp-mloop ; @true
diff --git a/sim/ft32/Makefile.in b/sim/ft32/Makefile.in
index 8a324af..a84512e 100644
--- a/sim/ft32/Makefile.in
+++ b/sim/ft32/Makefile.in
@@ -17,10 +17,6 @@
 
 ## COMMON_PRE_CONFIG_FRAG
 
-
-SIM_OBJS = \
-	$(SIM_NEW_COMMON_OBJS) \
-	interp.o	\
-	sim-resume.o
+SIM_LIBSIM =
 
 ## COMMON_POST_CONFIG_FRAG
diff --git a/sim/ft32/local.mk b/sim/ft32/local.mk
index 65a6817..2752f26 100644
--- a/sim/ft32/local.mk
+++ b/sim/ft32/local.mk
@@ -16,6 +16,24 @@
 ## You should have received a copy of the GNU General Public License
 ## along with this program.  If not, see <http://www.gnu.org/licenses/>.
 
+%C%_libsim_a_SOURCES =
+%C%_libsim_a_LIBADD = \
+	$(common_libcommon_a_OBJECTS) \
+	$(patsubst %,%D%/%,$(SIM_NEW_COMMON_OBJS)) \
+	$(patsubst %,%D%/dv-%.o,$(SIM_HW_DEVICES)) \
+	%D%/interp.o \
+	%D%/modules.o \
+	%D%/sim-resume.o
+$(%C%_libsim_a_OBJECTS) $(%C%_libsim_a_LIBADD): %D%/hw-config.h
+
+noinst_LIBRARIES += %D%/libsim.a
+
+%D%/%.o: %D%/%.c
+	$(AM_V_at)$(MAKE) $(AM_MAKEFLAGS) -C $(@D) $(@F)
+
+%D%/%.o: common/%.c
+	$(AM_V_at)$(MAKE) $(AM_MAKEFLAGS) -C $(@D) $(@F)
+
 %C%_run_SOURCES =
 %C%_run_LDADD = \
 	%D%/nrun.o \