aarch64: Try to avoid inappropriate default errors

After parsing a '{' and the first register, parse_typed_reg would
report errors in subsequent registers in the same way as for the
first register.  It used set_default_error, which reports errors
of the form "operand N must be X".

The problem is that if there are multiple opcode entries for the
same mnemonic, there could be several matches that lead to a
default error.  There's no guarantee that the default error for
the register list is the one that will be chosen.

To take an example from the testsuite:

    ext z0.b,{z31.b,z32.b},#0

gave:

    operand 2 must be an SVE vector register

with the error being reported against the single-vector version
of ext, even though the operand is clearly a list.

This patch uses set_fatal_syntax_error to bump the priority of the
error once we're sure that the operand is a list of the right type.

6 files changed, 26 insertions, 5 deletions

diff --git a/gas/config/tc-aarch64.c b/gas/config/tc-aarch64.c
index 596cc0f..616454b 100644
--- a/gas/config/tc-aarch64.c
+++ b/gas/config/tc-aarch64.c
@@ -1073,10 +1073,14 @@ parse_index_expression (char **str, int64_t *imm)
    FLAGS includes PTR_IN_REGLIST if the caller is parsing a register list.
 
    FLAGS includes PTR_FULL_REG if the function should ignore any potential
-   register index.  */
+   register index.
+
+   FLAGS includes PTR_GOOD_MATCH if we are sufficiently far into parsing
+   an operand that we can be confident that it is a good match.  */
 
 #define PTR_IN_REGLIST (1U << 0)
 #define PTR_FULL_REG (1U << 1)
+#define PTR_GOOD_MATCH (1U << 2)
 
 static const reg_entry *
 parse_typed_reg (char **ccp, aarch64_reg_type type,
@@ -1101,6 +1105,8 @@ parse_typed_reg (char **ccp, aarch64_reg_type type,
 	*typeinfo = atype;
       if (!isalpha && (flags & PTR_IN_REGLIST))
 	set_fatal_syntax_error (_("syntax error in register list"));
+      else if (flags & PTR_GOOD_MATCH)
+	set_fatal_syntax_error (NULL);
       else
 	set_default_error ();
       return NULL;
@@ -1109,7 +1115,10 @@ parse_typed_reg (char **ccp, aarch64_reg_type type,
   if (! aarch64_check_reg_type (reg, type))
     {
       DEBUG_TRACE ("reg type check failed");
-      set_default_error ();
+      if (flags & PTR_GOOD_MATCH)
+	set_fatal_syntax_error (NULL);
+      else
+	set_default_error ();
       return NULL;
     }
   type = reg->type;
@@ -1262,6 +1271,7 @@ parse_vector_reg_list (char **ccp, aarch64_reg_type type,
   int i;
   bool error = false;
   bool expect_index = false;
+  unsigned int ptr_flags = PTR_IN_REGLIST;
 
   if (*str != '{')
     {
@@ -1288,7 +1298,7 @@ parse_vector_reg_list (char **ccp, aarch64_reg_type type,
 	  val_range = val;
 	}
       const reg_entry *reg = parse_typed_reg (&str, type, &typeinfo,
-					      PTR_IN_REGLIST);
+					      ptr_flags);
       if (!reg)
 	{
 	  set_first_syntax_error (_("invalid vector register in list"));
@@ -1336,6 +1346,7 @@ parse_vector_reg_list (char **ccp, aarch64_reg_type type,
 	    nb_regs++;
 	  }
       in_range = 0;
+      ptr_flags |= PTR_GOOD_MATCH;
     }
   while (skip_past_comma (&str) || (in_range = 1, *str == '-'));
 
@@ -4530,13 +4541,14 @@ parse_sme_zero_mask(char **str)
   char *q;
   int mask;
   aarch64_opnd_qualifier_t qualifier;
+  unsigned int ptr_flags = PTR_IN_REGLIST;
 
   mask = 0x00;
   q = *str;
   do
     {
       const reg_entry *reg = parse_reg_with_qual (&q, REG_TYPE_ZA_ZAT,
-						  &qualifier, PTR_IN_REGLIST);
+						  &qualifier, ptr_flags);
       if (!reg)
 	return PARSE_FAIL;
 
@@ -4581,6 +4593,7 @@ parse_sme_zero_mask(char **str)
               return PARSE_FAIL;
             }
         }
+      ptr_flags |= PTR_GOOD_MATCH;
     }
   while (skip_past_char (&q, ','));
 
diff --git a/gas/testsuite/gas/aarch64/illegal-sve2.l b/gas/testsuite/gas/aarch64/illegal-sve2.l
index 2eab412..13df21b 100644
--- a/gas/testsuite/gas/aarch64/illegal-sve2.l
+++ b/gas/testsuite/gas/aarch64/illegal-sve2.l
@@ -255,7 +255,7 @@
 [^ :]+:[0-9]+: Error: invalid register list at operand 2 -- `ext z0\.b,{z0\.b,z31\.b},#0'
 [^ :]+:[0-9]+: Error: immediate value out of range 0 to 255 at operand 3 -- `ext z0\.b,{z0\.b,z1\.b},#256'
 [^ :]+:[0-9]+: Error: operand 1 must be an SVE vector register -- `ext z32\.b,{z0\.b,z1\.b},#0'
-[^ :]+:[0-9]+: Error: operand 2 must be an SVE vector register -- `ext z0\.b,{z31\.b,z32\.b},#0'
+[^ :]+:[0-9]+: Error: operand 2 must be a list of SVE vector registers -- `ext z0\.b,{z31\.b,z32\.b},#0'
 [^ :]+:[0-9]+: Error: operand 2 must be an SVE vector register -- `ext z0\.b,{z32\.b,z33\.b},#0'
 [^ :]+:[0-9]+: Error: operand 1 must be a SIMD vector register -- `faddp z32\.h,p0/m,z32\.h,z0\.h'
 [^ :]+:[0-9]+: Error: p0-p7 expected at operand 2 -- `faddp z0\.h,p8/m,z0\.h,z0\.h'
diff --git a/gas/testsuite/gas/aarch64/sme-4-illegal.l b/gas/testsuite/gas/aarch64/sme-4-illegal.l
index 72f6266..57d7d65 100644
--- a/gas/testsuite/gas/aarch64/sme-4-illegal.l
+++ b/gas/testsuite/gas/aarch64/sme-4-illegal.l
@@ -16,6 +16,8 @@
 [^:]*:[0-9]+: Error: missing ZA tile size at operand 1 -- `zero {za0}'
 [^:]*:[0-9]+: Error: syntax error in register list at operand 1 -- `zero {,za0.d}'
 [^:]*:[0-9]+: Error: syntax error in register list at operand 1 -- `zero {za0.d,}'
+[^:]*:[0-9]+: Error: operand 1 must be a list of 64-bit ZA element tiles -- `zero {za0.d,z1.d}'
+[^:]*:[0-9]+: Error: operand 1 must be a list of 64-bit ZA element tiles -- `zero {za0.d,za32.d}'
 [^:]*:[0-9]+: Error: syntax error in register list at operand 1 -- `zero {za0.d,za1.d,}'
 [^:]*:[0-9]+: Error: syntax error in register list at operand 1 -- `zero {za,}'
 [^:]*:[0-9]+: Error: unexpected character `}' in element size at operand 1 -- `zero {za.}'
diff --git a/gas/testsuite/gas/aarch64/sme-4-illegal.s b/gas/testsuite/gas/aarch64/sme-4-illegal.s
index 3d81942..da4aa3d 100644
--- a/gas/testsuite/gas/aarch64/sme-4-illegal.s
+++ b/gas/testsuite/gas/aarch64/sme-4-illegal.s
@@ -19,6 +19,8 @@ zero { , , }
 zero { za0 }
 zero { , za0.d }
 zero { za0.d , }
+zero { za0.d, z1.d }
+zero { za0.d, za32.d }
 zero { za0.d , za1.d , }
 zero { za, }
 zero { za. }
diff --git a/gas/testsuite/gas/aarch64/sve-invalid.l b/gas/testsuite/gas/aarch64/sve-invalid.l
index 930d673..b075093 100644
--- a/gas/testsuite/gas/aarch64/sve-invalid.l
+++ b/gas/testsuite/gas/aarch64/sve-invalid.l
@@ -1208,3 +1208,5 @@
 .*: Error: syntax error in register list at operand 1 -- `ld2b {.b},p0/z,\[x0\]'
 .*: Error: syntax error in register list at operand 1 -- `ld2b {z0.b-},p0/z,\[x0\]'
 .*: Error: syntax error in register list at operand 1 -- `ld2b {z0.b,},p0/z,\[x0\]'
+.*: Error: operand 1 must be a list of SVE vector registers -- `ld2b {z0\.b-z32\.b},p0/z,\[x0\]'
+.*: Error: operand 1 must be a list of SVE vector registers -- `ld2b {z0\.b-v1\.16b},p0/z,\[x0\]'
diff --git a/gas/testsuite/gas/aarch64/sve-invalid.s b/gas/testsuite/gas/aarch64/sve-invalid.s
index ece2142..b56a08d 100644
--- a/gas/testsuite/gas/aarch64/sve-invalid.s
+++ b/gas/testsuite/gas/aarch64/sve-invalid.s
@@ -1329,3 +1329,5 @@
 	ld2b	{.b}, p0/z, [x0]
 	ld2b	{z0.b-}, p0/z, [x0]
 	ld2b	{z0.b,}, p0/z, [x0]
+	ld2b	{z0.b-z32.b}, p0/z, [x0]
+	ld2b	{z0.b-v1.16b}, p0/z, [x0]