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path: root/sim/mn10300/interp.c
AgeCommit message (Expand)AuthorFilesLines
2023-12-19sim: mn10300: fix -Wunused-variable warningsMike Frysinger1-3/+0
2023-01-19sim: mn10300: minimize mn10300-sim.h include in sim-main.hMark Wielaard1-0/+3
2023-01-15sim: microblaze, mn10300: remove signal.h include in interp.cMark Wielaard1-2/+0
2022-12-25sim: cpu: change default init to handle all cpusMike Frysinger1-1/+1
2022-12-23sim: mn10300: standardize the arch-specific settings a littleMike Frysinger1-2/+0
2022-11-02sim: common: change sim_{fetch,store}_register helpers to use void* buffersMike Frysinger1-4/+4
2022-10-31sim: reg: constify store helperMike Frysinger1-3/+3
2022-01-06sim: mn10300: migrate to standard uintXX_t typesMike Frysinger1-3/+3
2021-11-15sim: split program path out of argv vectorMike Frysinger1-5/+1
2021-06-18sim: split sim-signal.h include outMike Frysinger1-0/+1
2021-06-17sim: overhaul & unify endian settings managementMike Frysinger1-0/+3
2021-05-29sim: mn10300: add SIGTRAP fallbackMike Frysinger1-0/+3
2021-05-16sim: switch config.h usage to defs.hMike Frysinger1-1/+3
2021-04-12sim: cgen: move cgen_cpu_max_extra_bytes logic into the common codeMike Frysinger1-1/+1
2021-02-06sim: watchpoints: use common sim_pc_getMike Frysinger1-1/+0
2021-01-30sim: watchpoints: change sizeof_pc to sizeof(sim_cia)Mike Frysinger1-1/+0
2021-01-11sim: clean up C11 header includesMike Frysinger1-10/+0
2016-01-06sim: sim_{create_inferior,open,parse_args}: constify argv/env slightlyMike Frysinger1-3/+3
2016-01-03sim: parse_args: display getopt error ourselvesMike Frysinger1-3/+1
2015-12-30sim: arm/d10v/h8300/m68hc11/microblaze/mips/mn10300/moxie/sh/v850: convert to...Mike Frysinger1-10/+9
2015-11-22sim: mn10300: drop global callback handleMike Frysinger1-6/+1
2015-11-15sim: sim-close: unify sim_close logicMike Frysinger1-8/+0
2015-06-11sim: mn10300: delete unused memory codeMike Frysinger1-47/+8
2015-06-11sim: mn10300: add missing static markingsMike Frysinger1-2/+2
2015-06-11sim: mn10300: delete unused exception/exited/debug stateMike Frysinger1-1/+0
2015-06-11sim: m68hc11/mn10300/v850: delete redundant INLINE definesMike Frysinger1-8/+0
2015-04-17sim: replace CIA_{GET,SET} with CPU_PC_{GET,SET}Mike Frysinger1-6/+6
2015-04-13sim: mn10300: convert to sim-cpuMike Frysinger1-6/+26
2015-03-24sim: m68hc11/mips/mn10300/v850: add basic sim_pc_getMike Frysinger1-0/+5
2012-06-17 * interp.c: Include config.h first. Do not include sysdep.h.Hans-Peter Nilsson1-1/+1
2012-02-16Update sim_fetch_register, sim_store_register for sh and mn10300.Kevin Buettner1-1/+1
2011-07-05sim: start a unified sim_do_commandMike Frysinger1-17/+0
2011-01-11http://sourceware.org/ml/gdb-patches/2010-11/msg00112.htmlAndrew Burgess1-1/+1
2004-06-262000-08-07 Graham Stott <grahams@cygnus.co.uk>Alexandre Oliva1-0/+569
2004-06-26* interp.c, mn10300_sim.h, op_utils.c: Convert function prototypesAlexandre Oliva1-54/+36
2004-06-26* configure.in: Use common simulator always. Don't subst sim_genAlexandre Oliva1-856/+0
2003-02-27Index: arm/ChangeLogAndrew Cagney1-4/+4
1999-07-19import gdb-1999-07-19 snapshotJason Molenda1-4/+4
1999-04-26import gdb-19990422 snapshotStan Shebs1-4/+24
1999-04-16Initial creation of sourceware repositorygdb-4_18-branchpointStan Shebs1-0/+1402
1999-04-16Initial creation of sourceware repositoryStan Shebs1-1402/+0
1998-12-30* eCos->devo merge; am30 sanitization tags removedFrank Ch. Eigler1-113/+254
1998-06-19Fri Jun 19 11:59:26 1998 Joyce Janczyn <janczyn@cygnus.com>Joyce Janczyn1-1/+1
1998-06-18Thu June 18 14:37:14 1998 Joyce Janczyn <janczyn@cygnus.com>Joyce Janczyn1-1/+4
1998-06-08 * interp.c: (mn10300_option_handler): New function parses argumentsJoyce Janczyn1-114/+156
1998-03-27Add sanitize-am30 markers. Keep details of AM30 implementation ofAndrew Cagney1-24/+30
1998-03-25* interp.c (sim_open): Create second 1mb memory region at 0x40000000.Andrew Cagney1-150/+119
1998-03-25Pacify GCC.Andrew Cagney1-3/+4
1998-03-24Add code to support building mn10300 simulator with the common simulatorJoyce Janczyn1-79/+398
1997-08-26Flush defunct sim_kill.Andrew Cagney1-7/+0
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