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AgeCommit message (Expand)AuthorFilesLines
2022-12-25sim: cpu: change default init to handle all cpusMike Frysinger1-1/+1
2022-12-25sim: m32r: fix iterator typo when setting up cpusMike Frysinger1-1/+1
2022-12-23sim: m32r: move arch-specific settings to internal headerMike Frysinger7-22/+33
2022-12-23sim: lm32/m32r: drop redundant opcode/cgen.h includeMike Frysinger1-1/+0
2022-12-23sim: cgen: move symcat.h include to where it's usedMike Frysinger2-1/+2
2022-12-23sim: cgen: move cgen-types.h include to cgen-defs.hMike Frysinger1-1/+0
2022-12-22sim: use bfd_vma when reading start addr from bfd infoMike Frysinger1-1/+1
2022-12-22sim: m32r: include sim-hw.h for sim_hw_parseMike Frysinger1-0/+1
2022-12-21sim: build: hoist lists of hw devices upMike Frysinger2-4/+5
2022-12-21sim: enable common sim_cpu usage everywhereMike Frysinger1-2/+0
2022-12-21sim: m32r: invert sim_cpu storageMike Frysinger5-14/+10
2022-11-05sim: run: move linking into top-levelMike Frysinger1-0/+8
2022-11-04sim: build: remove various obsolete generation dep variablesMike Frysinger1-6/+0
2022-11-02sim: common: change sim_{fetch,store}_register helpers to use void* buffersMike Frysinger3-6/+6
2022-10-31sim: reg: constify store helperMike Frysinger3-3/+3
2022-10-29sim/m32r: Initialize "list" variableTsukasa OI1-1/+1
2022-05-13sim: remove use of PTRAlan Modra1-2/+2
2022-01-01Automatic Copyright Year update after running gdb/copyright.pyJoel Brobecker37-37/+37
2021-12-09sim: use ## for automake commentsMike Frysinger1-21/+21
2021-11-16sim: callback: expose argv & environMike Frysinger1-3/+8
2021-11-16sim: keep track of program environment stringsMike Frysinger1-1/+7
2021-11-15sim: split program path out of argv vectorMike Frysinger1-5/+1
2021-11-02sim: hoist cgen mloop rules up to common buildsMike Frysinger2-56/+66
2021-11-01sim: m32r: reduce -Wno-error scopeMike Frysinger1-2/+2
2021-10-31sim: drop unused targ-vals.h includesMike Frysinger1-1/+0
2021-10-31sim: tighten up stamp rulesMike Frysinger1-3/+6
2021-10-31sim: silence stamp touch rulesMike Frysinger1-7/+7
2021-10-31sim: standardize move-if-change rulesMike Frysinger1-6/+6
2021-08-22sim: m32r: add __linux__ hack for non-Linux hostsMike Frysinger1-0/+8
2021-08-17sim: rename ChangeLog files to ChangeLog-2021Mike Frysinger1-0/+0
2021-07-01sim: m32r: merge with common configure scriptMike Frysinger4-2896/+6
2021-07-01sim: m32r: reformat linux traps codeMike Frysinger2-1067/+1067
2021-07-01sim: m32r: unify ELF & Linux traps logicMike Frysinger8-1385/+1207
2021-07-01sim: m32r: replace custom endian helpers with sim-endianMike Frysinger2-107/+90
2021-07-01sim: m32r: fix virtual environment with Linux targetsMike Frysinger2-8/+8
2021-07-01sim: m32r: namespace Linux syscall tableMike Frysinger3-370/+377
2021-06-30sim: unify scache settingsMike Frysinger4-34/+7
2021-06-30sim: move default model to the runtime sim stateMike Frysinger5-24/+9
2021-06-30sim: namespace sim_machsMike Frysinger3-1/+11
2021-06-29sim: model: constify sim_machs storageMike Frysinger2-1/+5
2021-06-28sim: cgen: delete unused record_trace_results functionsMike Frysinger4-24/+6
2021-06-24sim: callback: extend syscall interface to handle 7 argsMike Frysinger2-0/+8
2021-06-22sim: drop configure scripts for simple portsMike Frysinger2-0/+11
2021-06-21sim: unify hardware settingsMike Frysinger3-49/+5
2021-06-21sim: hw: rework configure option & device selectionMike Frysinger4-39/+32
2021-06-20sim: delete SIM_AC_COMMON macroMike Frysinger4-5/+5
2021-06-20sim: unify general maintainer settingsMike Frysinger3-124/+5
2021-06-20sim: unify cgen maintainer settingsMike Frysinger5-45/+6
2021-06-20sim: move sim-inline to the common codeMike Frysinger3-36/+5
2021-06-19sim: unify gettext/intl probing logicMike Frysinger2-85/+0
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