| Age | Commit message (Expand) | Author | Files | Lines |
|---|
| 2021-05-29 | MIPS/opcodes: Do not use CP0 register names for control registers | Maciej W. Rozycki | 4 | -17/+39 |
| 2021-05-29 | MIPS/opcodes: Add TX39 CP0 register names | Maciej W. Rozycki | 2 | -1/+19 |
| 2021-05-29 | MIPS/opcodes: Free up redundant `g' operand code | Maciej W. Rozycki | 2 | -4/+9 |
| 2021-05-29 | microMIPS/opcodes: Refer FPRs rather than FCRs with DMTC1 | Maciej W. Rozycki | 2 | -1/+6 |
| 2021-05-27 | PowerPC: Add new xxmr and xxlnot extended mnemonics | Peter Bergner | 2 | -0/+6 |
| 2021-05-25 | Regen cris files | Alan Modra | 5 | -30/+67 |
| 2021-05-24 | opcodes: cris: move desc & opc files from sim/ | Mike Frysinger | 9 | -4/+3403 |
| 2021-05-18 | RISC-V: PR27814, Objdump crashes when disassembling a non-ELF RISC-V binary. | Job Noorman | 2 | -10/+20 |
| 2021-05-17 | arm: Fix bugs with MVE vmov from two GPRs to vector lanes | Alex Coplan | 2 | -2/+14 |
| 2021-05-11 | Fix an illegal memory access when attempting to disassemble a corrupt TIC30 b... | Nick Clifton | 2 | -0/+9 |
| 2021-05-06 | or1k: Implement relocation R_OR1K_GOT_AHI16 for gotha() | Stafford Horne | 2 | -1/+11 |
| 2021-05-01 | opcodes: xtensa: support branch visualization | Max Filippov | 2 | -0/+15 |
| 2021-04-26 | x86: optimize LEA | Jan Beulich | 3 | -2/+7 |
| 2021-04-23 | opcodes: xtensa: display loaded literal value | Max Filippov | 2 | -1/+24 |
| 2021-04-23 | opcodes: xtensa: improve literal output | Max Filippov | 2 | -0/+6 |
| 2021-04-19 | aarch64: New instructions for maintenance of GPT entries cached in a TLB | Przemyslaw Wirkus | 2 | -0/+10 |
| 2021-04-19 | aarch64: Add new data cache maintenance operations | Przemyslaw Wirkus | 2 | -0/+7 |
| 2021-04-19 | arm64: add two initializers | Jan Beulich | 2 | -2/+8 |
| 2021-04-16 | aarch64: Define RME system registers | Przemyslaw Wirkus | 2 | -0/+8 |
| 2021-04-16 | Update the ChangeLog, and add the missing entries. | Nelson Chu | 1 | -0/+5 |
| 2021-04-16 | RISC-V: compress "addi d,CV,z" to "c.mv d,CV" | Lifang Xia | 1 | -0/+1 |
| 2021-04-13 | ENABLE_CHECKING in bfd, opcodes, binutils, ld | Alan Modra | 4 | -2/+42 |
| 2021-04-09 | AArch64: Fix Atomic LD64/ST64 classification. | Tejas Belagod | 2 | -4/+9 |
| 2021-04-09 | PowerPC disassembly of pcrel references | Alan Modra | 2 | -10/+143 |
| 2021-04-08 | PR27684, PowerPC missing mfsprg0 and others | Alan Modra | 2 | -4/+10 |
| 2021-04-08 | PR27676, PowerPC missing extended dcbt, dcbtst mnemonics | Alan Modra | 2 | -7/+90 |
| 2021-04-06 | Return symbol from symbol_at_address_func | Alan Modra | 3 | -23/+14 |
| 2021-04-05 | C99 opcodes configury | Alan Modra | 8 | -1248/+528 |
| 2021-04-01 | Remove strneq macro and use startswith. | Martin Liska | 5 | -18/+9 |
| 2021-04-01 | PR27675, PowerPC missing extended mnemonic mfummcr2 | Alan Modra | 2 | -0/+7 |
| 2021-03-31 | Use bool in opcodes | Alan Modra | 49 | -1573/+1591 |
| 2021-03-31 | Remove bfd_stdint.h | Alan Modra | 12 | -11/+25 |
| 2021-03-30 | x86: drop seg_entry | Jan Beulich | 3 | -21/+17 |
| 2021-03-30 | x86: drop REGNAM_{AL,AX,EAX} | Jan Beulich | 2 | -5/+4 |
| 2021-03-30 | x86: adjust st(<N>) parsing | Jan Beulich | 4 | -12/+13 |
| 2021-03-29 | x86: move some opcode table entries | Jan Beulich | 3 | -489/+500 |
| 2021-03-29 | x86: VPSADBW's source operands are also commutative | Jan Beulich | 3 | -6/+12 |
| 2021-03-29 | x86: fold SSE2AVX and their base MMX/SSE templates | Jan Beulich | 4 | -924/+645 |
| 2021-03-29 | x86: undo Prefix_0X<nn> use in opcode table | Jan Beulich | 3 | -375/+383 |
| 2021-03-29 | x86: shrink some struct insn_template fields | Jan Beulich | 2 | -4/+10 |
| 2021-03-29 | x86: derive opcode encoding space attribute from base opcode | Jan Beulich | 3 | -1601/+1641 |
| 2021-03-29 | TRUE/FALSE simplification | Alan Modra | 5 | -54/+68 |
| 2021-03-29 | opcodes int vs bfd_boolean fixes | Alan Modra | 3 | -10/+15 |
| 2021-03-26 | x86-64: don't accept supposedly disabled MOVQ forms | Jan Beulich | 3 | -4/+10 |
| 2021-03-25 | [NIOS2] Fix disassembly of br.n instruction. | Hafiz Abid Qadeer | 2 | -1/+6 |
| 2021-03-25 | x86: flag bad S/G insn operand combinations | Jan Beulich | 3 | -16/+86 |
| 2021-03-25 | x86: flag as bad AVX512 insns with EVEX.z set but EVEX.aaa clear | Jan Beulich | 2 | -0/+12 |
| 2021-03-25 | x86: fix AMD Zen3 insns | Jan Beulich | 3 | -4/+66 |
| 2021-03-25 | PR27647 PowerPC extended conditional branch mnemonics | Alan Modra | 2 | -476/+486 |
| 2021-03-24 | x86: derive opcode length from opcode value | Jan Beulich | 5 | -7463/+7468 |
