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2021-07-26PATCH [4/10] arm: add 'pac' instruction for Armv8.1-M pacbti extensionAndrea Corallo1-0/+2
2021-07-26PATCH [3/10] arm: add 'aut' instruction for Armv8.1-M pacbti extensionAndrea Corallo1-0/+2
2021-07-26PATCH [2/10] arm: add 'pacbti' instruction for Armv8.1-M pacbti extensionAndrea Corallo1-0/+2
2021-07-26PATCH [1/10] arm: add 'bti' instruction for Armv8.1-M pacbti extensionAndrea Corallo1-0/+5
2021-07-23x86: express unduly set rounding control bits in disassemblyJan Beulich1-37/+53
2021-07-22x86: drop dq{b,d}_modeJan Beulich1-30/+13
2021-07-22x86: drop vex_scalar_w_dq_modeJan Beulich3-51/+41
2021-07-22x86: drop xmm_m{b,w,d,q}_modeJan Beulich4-164/+91
2021-07-22x86: fold duplicate vector register printing codeJan Beulich1-74/+33
2021-07-22x86: drop vex_mode and vex_scalar_modeJan Beulich1-11/+7
2021-07-22x86: correct EVEX.V' handling outside of 64-bit modeJan Beulich1-4/+16
2021-07-22x86: fold duplicate code in MOVSXD_Fixup()Jan Beulich1-16/+10
2021-07-22x86: fold duplicate register printing codeJan Beulich1-105/+14
2021-07-22x86-64: properly bounds-check %bnd<N> in OP_G()Jan Beulich1-1/+1
2021-07-22x86-64: generalize OP_G()'s EVEX.R' handlingJan Beulich1-1/+8
2021-07-22x86: correct VCVT{,U}SI2SD rounding mode handlingJan Beulich3-15/+3
2021-07-22x86: drop OP_Mask()Jan Beulich4-48/+28
2021-07-14x86: Add int1 as one byte opcode 0xf1H.J. Lu3-1/+15
2021-07-07Add changelog entries for last commitAndreas Krebbel1-0/+4
2021-07-07IBM Z: Add another arch14 instructionAndreas Krebbel1-0/+2
2021-07-05Updated translations (mainly Ukranian and French) triggered by creation of 2....Nick Clifton3-709/+868
2021-07-03Update version number and regenerate filesNick Clifton3-220/+254
2021-07-03Add markers for 2.37 branchNick Clifton1-0/+4
2021-07-02Re: Fix minor NDS32 renaming snafuAlan Modra3-12/+21
2021-07-01cgen: split GUILE setting outMike Frysinger3-2/+10
2021-07-01opcodes: constify & local meps macrosMike Frysinger2-5/+12
2021-07-01opcodes: cleanup nds32 variablesMike Frysinger3-40/+57
2021-07-01opcodes: constify & localize z80 opcodesMike Frysinger2-2/+7
2021-07-01opcodes: constify & scope microblaze opcodesMike Frysinger3-11/+23
2021-07-01opcodes: constify aarch64_opcode_tablesMike Frysinger3-3/+8
2021-06-22opcodes: make use of __builtin_popcount when availableAndrew Burgess2-0/+9
2021-06-22picojava assembler and disassembler fixesAlan Modra2-2/+8
2021-06-19ubsan: vax: pointer overflowAlan Modra2-1/+5
2021-06-19Fix another strncpy warningAlan Modra2-1/+6
2021-06-17powerpc: move cell "or rx,rx,rx" hintsAlan Modra2-5/+10
2021-06-03PR1202, mcore disassembler: wrong address looptAlan Modra2-4/+10
2021-06-02arc: Construct disassembler options dynamicallyShahab Vahedi2-27/+161
2021-05-29PowerPC table driven -Mraw disassemblyAlan Modra3-1635/+1634
2021-05-29MIPS/opcodes: Reorder legacy COP0, COP2, COP3 opcode instructionsMaciej W. Rozycki2-66/+73
2021-05-29MIPS/opcodes: Accurately record coprocessor opcode CPU/ISA membershipMaciej W. Rozycki2-51/+61
2021-05-29MIPS/opcodes: Remove DMFC3 and DMTC3 instructionsMaciej W. Rozycki2-4/+5
2021-05-29MIPS/opcodes: Disassemble the RFE instructionMaciej W. Rozycki2-2/+8
2021-05-29MIPS/opcodes: Add legacy CP1 control register namesMaciej W. Rozycki2-25/+47
2021-05-29MIPS/opcodes: Do not use CP0 register names for control registersMaciej W. Rozycki4-17/+39
2021-05-29MIPS/opcodes: Add TX39 CP0 register namesMaciej W. Rozycki2-1/+19
2021-05-29MIPS/opcodes: Free up redundant `g' operand codeMaciej W. Rozycki2-4/+9
2021-05-29microMIPS/opcodes: Refer FPRs rather than FCRs with DMTC1Maciej W. Rozycki2-1/+6
2021-05-27PowerPC: Add new xxmr and xxlnot extended mnemonicsPeter Bergner2-0/+6
2021-05-25Regen cris filesAlan Modra5-30/+67
2021-05-24opcodes: cris: move desc & opc files from sim/Mike Frysinger9-4/+3403
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