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2023-03-30aarch64: Add the SME2 multivector LD1 and ST1 instructionsRichard Sandiford10-448/+2088
2023-03-30aarch64: Add the SME2 MOVA instructionsRichard Sandiford10-312/+674
2023-03-30aarch64: Add support for predicate-as-counter registersRichard Sandiford6-1597/+1647
2023-03-30aarch64; Add support for vector offset rangesRichard Sandiford1-9/+48
2023-03-30aarch64: Add support for vgx2 and vgx4Richard Sandiford1-8/+41
2023-03-30aarch64: Add _off4 suffix to AARCH64_OPND_SME_ZA_arrayRichard Sandiford3-7/+7
2023-03-30aarch64: Add a _10 suffix to FLD_imm3Richard Sandiford6-8/+8
2023-03-30aarch64: Prefer register ranges & support wrappingRichard Sandiford1-1/+1
2023-03-30aarch64: Add support for strided register listsRichard Sandiford2-23/+56
2023-03-30aarch64: Sort fields alphanumericallyRichard Sandiford2-163/+164
2023-03-30aarch64: Resync field namesRichard Sandiford1-7/+7
2023-03-30aarch64: Regularise FLD_* suffixesRichard Sandiford6-55/+55
2023-03-30aarch64: Add a aarch64_cpu_supports_inst_p helperRichard Sandiford1-0/+13
2023-03-30aarch64: Reorder some OP_SVE_* macrosRichard Sandiford1-16/+16
2023-03-30aarch64: Rename aarch64-tbl.h OP_SME_* macrosRichard Sandiford1-81/+77
2023-03-30aarch64: Try to report invalid variants against the closest matchRichard Sandiford3-19/+30
2023-03-30aarch64: Make AARCH64_OPDE_REG_LIST take a bitfieldRichard Sandiford1-1/+1
2023-03-30aarch64: Add an operand class for SVE register listsRichard Sandiford3-14/+13
2023-03-30aarch64: Commonise checks for index operandsRichard Sandiford1-18/+32
2023-03-30aarch64: Add an error code for out-of-range registersRichard Sandiford1-6/+14
2023-03-30aarch64: Move w12-w15 range check to libopcodesRichard Sandiford1-6/+20
2023-03-30aarch64: Move ZA range checks to aarch64-opc.cRichard Sandiford3-25/+67
2023-03-30aarch64: Make indexed_za use 64-bit immediatesRichard Sandiford1-3/+3
2023-03-30aarch64: Rename za_tile_vector to za_indexRichard Sandiford3-36/+36
2023-03-30aarch64: Treat ZA as a registerRichard Sandiford2-2/+2
2023-03-30aarch64: Make SME instructions use F_STRICTRichard Sandiford3-57/+62
2023-03-30aarch64: Restrict range of PRFM opcodesRichard Sandiford1-0/+9
2023-03-30aarch64: Fix PSEL opcode maskRichard Sandiford1-1/+1
2023-03-30aarch64: Add sme-i16i64 and sme-f64f64 aliasesRichard Sandiford1-22/+22
2023-03-21RISC-V: Fix disassemble fetch fail return value.Jiawei1-2/+2
2023-03-20x86: drop "shimm" special case template expansionsJan Beulich1-15/+15
2023-03-20x86: VexVVVV is now merely a booleanJan Beulich3-260/+247
2023-03-20x86: re-work build_modrm_byte()'s register assignmentJan Beulich2-57/+57
2023-03-20Revert "segfault at i386-dis.c:9815"Alan Modra1-9/+4
2023-03-19segfault at i386-dis.c:9815Alan Modra1-4/+9
2023-03-16cpu/mem.opc whitespace tidyAlan Modra2-24/+23
2023-03-15Fix an illegal memory access when disassembling a corrupt MeP file.Nick Clifton2-0/+19
2023-03-15Fix an illegal memory access when disassebling a corrupt ARM file.Nick Clifton2-5/+17
2023-02-28[Aarch64] Add Binutils support for MECRichard Ball2-0/+13
2023-02-27Updated Serbian translations for gold, gprof and opcodes sub-directoriesNick Clifton1-300/+301
2023-02-25opcodes/m68k: enable libopcodes styling for GDBAndrew Burgess1-0/+5
2023-02-24x86: MONITOR/MWAIT are not SSE3 insnsJan Beulich5-7148/+7161
2023-02-24x86-64: don't permit LAHF/SAHF with "generic64"Jan Beulich5-5127/+5166
2023-02-24x86: have insns acting on segment selector values allow for consistent operandsJan Beulich2-897/+964
2023-02-24x86: restrict insn templates accepting negative 8-bit immediatesJan Beulich2-154/+154
2023-02-22x86-64: LAR and LSL don't need REX.WJan Beulich2-8/+8
2023-02-22x86: optimize BT{,C,R,S} $imm,%regJan Beulich2-8/+8
2023-02-20opcodes: style m68k disassembler outputAndreas Schwab1-116/+238
2023-02-14x86: {LD,ST}TILECFG use an extension opcodeJan Beulich2-4/+4
2023-02-13PR30120: fix x87 fucomp misassembledMichael Matz2-2/+2
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