aboutsummaryrefslogtreecommitdiff
path: root/opcodes
AgeCommit message (Expand)AuthorFilesLines
2022-07-21x86: replace wrong attributes on VCVTDQ2PH{X,Y}Jan Beulich2-4/+4
2022-07-21x86/Intel: correct AVX512F scatter insn element sizesJan Beulich2-8/+8
2022-07-20Re: opcodes/arc: Implement style support in the disassemblerAlan Modra1-1/+1
2022-07-18opcodes/arc: Implement style support in the disassemblerClaudiu Zissulescu3-46/+117
2022-07-18x86: correct VMOVSH attributesJan Beulich2-5/+5
2022-07-18x86: re-order insn template fieldsJan Beulich3-3720/+3728
2022-07-09Regenerate with automake-1.15.1Alan Modra3-901/+422
2022-07-08libopcodes/s390: add support for disassembler stylingAndrew Burgess2-16/+72
2022-07-08Update version to 2.39.50 and regenerate filesNick Clifton4-590/+1026
2022-07-08Add markers for 2.39 branchNick Clifton1-0/+4
2022-07-07RISC-V: Added Zfhmin and Zhinxmin.Tsukasa OI1-63/+63
2022-07-07RISC-V: Fix disassembling Zfinx with -M numericTsukasa OI1-1/+1
2022-07-06x86: make D attribute usable for XOP and FMA4 insnsJan Beulich3-706/+62
2022-07-04opcodes/avr: Implement style support in the disassemblerMarcus Nilsson3-10/+55
2022-07-04x86: fold Disp32S and Disp32Jan Beulich5-12883/+12886
2022-07-04x86: restore masking of displacement kindsJan Beulich2-12/+12
2022-06-29opcodes/aarch64: split off creation of comment text in disassemblerAndrew Burgess2-8/+29
2022-06-29x86: drop stray NoRex64 from XBEGINJan Beulich2-2/+2
2022-06-27drop XC16x bitsJan Beulich14-10784/+4
2022-06-22RISC-V: Use single h extension to control hypervisor CSRs and instructions.Nelson Chu1-19/+19
2022-06-15x86: drop print_operand_value()'s "hex" parameterJan Beulich1-55/+16
2022-06-13x86: fix incorrect indirectionJan Beulich1-1/+1
2022-06-13x86: replace global scratch bufferJan Beulich1-126/+97
2022-06-13x86: avoid string copy when swapping Vex.W controlled operandsJan Beulich1-6/+8
2022-06-13x86: shrink prefix related disassembler state fieldsJan Beulich1-27/+28
2022-06-13x86: properly initialize struct instr_info instance(s)Jan Beulich1-257/+235
2022-06-08libopcodes: extend the styling within the i386 disassemblerAndrew Burgess1-137/+286
2022-05-30RISC-V: Add zhinx extension supports.jiawei1-56/+56
2022-05-27opcodes/i386: remove trailing whitespace from insns with zero operandsAndrew Burgess1-5/+22
2022-05-27Remove use of bfd_uint64_t and similarAlan Modra3-4/+4
2022-05-27x86: re-work AVX512 embedded rounding / SAEJan Beulich2-11453/+853
2022-05-27x86/Intel: adjust representation of embedded rounding / SAEJan Beulich1-0/+17
2022-05-27x86/Intel: adjust representation of embedded broadcastJan Beulich1-4/+11
2022-05-25opcodes: introduce BC field; fix iselDmitry Selyutin1-2/+5
2022-05-25ppc: extend opindex to 16 bitsDmitry Selyutin1-6/+6
2022-05-20RISC-V: Update zfinx implement with zicsr.Jia-Wei Chen1-14/+14
2022-05-20RISC-V: Remove RV128-only fmv instructionsTsukasa OI1-2/+0
2022-05-18x86: shrink op_riprelJan Beulich1-18/+12
2022-05-17RISC-V: Added half-precision floating-point v1.0 instructions.Nelson Chu1-0/+65
2022-05-12cgen: increase buffer for hash_insn_listAlan Modra1-5/+5
2022-05-11opcodes cgen: remove use of PTRAlan Modra29-1290/+1284
2022-05-10opcodes: remove use of PTRAlan Modra6-6/+6
2022-05-07Fix multiple ubsan warnings in i386-dis.cAlan Modra1-13/+13
2022-05-05Move TILE-Gx files to TARGET64_LIBOPCODES_CFILESLuis Machado2-6/+6
2022-05-05Don't define ARCH_cris for BFD64Luis Machado1-1/+1
2022-05-05IBM zSystems: mgrk, mg first operand requires register pairAndreas Krebbel2-2/+4
2022-04-30opcodes: don't assume ELF in riscv, csky, rl78, mep disassemblersThomas Hebb4-23/+22
2022-04-27x86: VFPCLASSSH is Evex.LLIGJan Beulich2-3/+2
2022-04-19x86: VCMPSH is Evex.LLIGJan Beulich2-98/+98
2022-04-19x86: drop stray CheckRegSize from VFPCLASSPHJan Beulich2-2/+2
generated by cgit v1.1 at 2024-11-10 16:33:49 +0000