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2023-07-14Fix loongarch build with gcc-4.5Alan Modra1-1/+1
2023-07-11x86: simplify table-referencing macrosJan Beulich1-17/+15
2023-07-11x86: convert 0FXOP to just XOP in enumerator namesJan Beulich1-304/+304
2023-07-11x86: misc further register-only insns don't need to go through mod_table[]Jan Beulich4-163/+77
2023-07-11x86: various operations on mask registers can avoid going through mod_table[]Jan Beulich4-296/+176
2023-07-11x86: slightly rework handling of some register-only insnsJan Beulich2-62/+53
2023-07-11x86: SIMD shift-by-immediate don't need to go through mod_table[]Jan Beulich1-54/+18
2023-07-11x86: misc further memory-only insns don't need to go through mod_table[]Jan Beulich6-315/+124
2023-07-11x86: {,V}MOVNT* don't need to go through mod_table[]Jan Beulich3-64/+18
2023-07-11x86: fold legacy/VEX {,V}MOV{H,L}* entriesJan Beulich2-68/+34
2023-07-11x86: fold certain legacy/VEX table entriesJan Beulich2-305/+109
2023-07-04x86: optimize 128-bit VPBROADCASTQ to VPUNPCKLQDQJan Beulich2-3/+3
2023-07-04x86: optimize pre-AVX512 {,V}PCMPGT* with identical sourcesJan Beulich2-21/+21
2023-07-04x86: optimize pre-AVX512 {,V}PCMPEQQ with identical sourcesJan Beulich2-5/+5
2023-07-04x86: flag bad EVEX masking for miscellaneous insnsJan Beulich6-44/+51
2023-07-04x86: flag EVEX masking when destination is GPR(-like)Jan Beulich1-1/+16
2023-07-04x86: flag EVEX.z set when destination is memoryJan Beulich1-0/+7
2023-07-04x86: flag EVEX.z set when destination is a mask registerJan Beulich1-0/+12
2023-07-04x86: re-work EVEX-z-without-masking checkJan Beulich1-10/+8
2023-07-04Updated Ukranian, Romanian and German translations for various sub-directoriesNick Clifton2-747/+679
2023-07-04arc: Update neg<.f> 0,b encodingClaudiu Zissulescu1-1/+1
2023-07-03Change version number to 2.41.50 and regenerate filesNick Clifton3-375/+211
2023-07-03Add markers for the 2.41 branchNick Clifton1-0/+4
2023-07-03opcodes/loongarch: Mark address offset operands of LVZ/LBT insns as suchWANG Xuerui1-28/+28
2023-07-01RISC-V: Add support for the Zvksh ISA extensionChristoph Müllner1-0/+4
2023-07-01RISC-V: Add support for the Zvksed ISA extensionChristoph Müllner1-0/+5
2023-07-01RISC-V: Add support for the Zvknh[a,b] ISA extensionsChristoph Müllner1-0/+5
2023-07-01RISC-V: Add support for the Zvkned ISA extensionChristoph Müllner1-0/+13
2023-07-01RISC-V: Add support for the Zvkg ISA extensionChristoph Müllner1-0/+4
2023-07-01RISC-V: Add support for the Zvbc extensionNathan Huckleberry1-0/+6
2023-07-01RISC-V: Add support for the Zvbb ISA extensionChristoph Müllner2-0/+22
2023-06-30RISC-V: Add support for the Zfa extensionChristoph Müllner2-0/+80
2023-06-30LoongArch: gas: Fix code style issuesmengqinggang1-1682/+1681
2023-06-30LoongArch: gas: Add LVZ and LBT instructions supportmengqinggang2-2/+200
2023-06-30LoongArch: Deprecate $v[01], $fv[01] and $x names per specWANG Xuerui1-4/+4
2023-06-30opcodes/loongarch: print unrecognized insn words with the .word directiveWANG Xuerui1-0/+1
2023-06-30opcodes/loongarch: do not print hex notation for signed immediatesWANG Xuerui1-7/+1
2023-06-30opcodes/loongarch: style disassembled address offsets as suchWANG Xuerui2-28/+41
2023-06-30opcodes/loongarch: implement style support in the disassemblerWANG Xuerui2-23/+27
2023-06-30opcodes/loongarch: remove unused codeWANG Xuerui1-35/+0
2023-06-30LoongArch: support disassembling certain pseudo-instructionsWANG Xuerui2-11/+38
2023-06-28aarch64: Remove version dependencies from featuresAndrew Carlotti1-17/+19
2023-06-28LoongArch: gas: Add lsx and lasx instructions supportmengqinggang1-0/+1465
2023-06-27 RISC-V: Support Zicond extensionPhilipp Tomsich1-0/+4
2023-06-25LoongArch: Support referring to FCSRs as $fcsrXFeiyang Chen2-3/+22
2023-06-21x86: fix expansion of %XVJan Beulich1-7/+8
2023-06-16x86: shrink Masking insn attribute to a single bit (boolean)Jan Beulich3-1635/+1627
2023-06-15Add additional missing Allegrex CPU instructionsDavid Guillen Fandos1-14/+24
2023-06-15Add rotation instructions to MIPS Allegrex CPUDavid Guillen Fandos1-7/+7
2023-06-15Add MIPS Allegrex CPU as a MIPS2-based CPUDavid Guillen Fandos2-26/+32
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