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path: root/opcodes/i386-tbl.h
AgeCommit message (Expand)AuthorFilesLines
2018-10-05x86: Add Intel ENCLV to assembler and disassemblerH.J. Lu1-0/+14
2018-07-18x86: Split vcvtps2{,u}qq and vcvttps2{,u}qqH.J. Lu1-8/+76
2018-06-01x86: fold MOV to/from segment register templatesJan Beulich1-109/+7
2018-06-01x86: don't emit REX.W for SLDT and STRJan Beulich1-2/+2
2018-06-01x86/Intel: accept "oword ptr" for INVPCIDJan Beulich1-4/+4
2018-05-07Enable Intel MOVDIRI, MOVDIR64B instructionsH.J. Lu1-4962/+5013
2018-04-27Revert "Enable Intel MOVDIRI, MOVDIR64B instructions."Igor Tsimbalist1-15010/+14942
2018-04-26Enable Intel MOVDIRI, MOVDIR64B instructions.Igor Tsimbalist1-14942/+15010
2018-04-26x86: fold various non-memory operand AVX512VL templatesJan Beulich1-1800/+416
2018-04-26x86: drop CpuRegMMX, CpuReg[XYZ]MM, and CpuRegMaskJan Beulich1-5039/+5039
2018-04-26x86: drop VexImmExtJan Beulich1-8001/+8001
2018-04-25x86: drop redundant AVX512VL shift templatesJan Beulich1-120/+0
2018-04-17Enable Intel CLDEMOTE instruction.Igor Tsimbalist1-5044/+5058
2018-04-15x86: Allow 32-bit registers for tpause and umwaitH.J. Lu1-32/+4
2018-04-11Enable Intel WAITPKG instructions.Igor Tsimbalist1-5040/+5124
2018-03-28x86: drop VecESizeJan Beulich1-7385/+7385
2018-03-28x86: convert broadcast insn attribute to booleanJan Beulich1-885/+885
2018-03-28x86: fold to-scalar-int conversion insnsJan Beulich1-444/+56
2018-03-22x86: drop pointless VecESizeJan Beulich1-475/+475
2018-03-22x86: fix swapped operand handling for BNDMOVJan Beulich1-2/+2
2018-03-22x86/Intel: fix fallout from earlier template foldingJan Beulich1-15/+100
2018-03-22x86: fold a few XOP templatesJan Beulich1-220/+36
2018-03-08x86-64: Also optimize "clr reg64"H.J. Lu1-1/+1
2018-03-08x86: Remove support for old (<= 2.8.1) versions of gccH.J. Lu1-5225/+5089
2018-03-08x86: fold several AVX512VL templatesJan Beulich1-1867/+259
2018-03-08x86: fold certain AVX512 rotate and shift templatesJan Beulich1-870/+90
2018-03-08x86: fold VEX-encoded GFNI templatesJan Beulich1-78/+12
2018-03-08x86: fold a few AVX512F templatesJan Beulich1-216/+12
2018-03-08x86: fold LWP templatesJan Beulich1-78/+10
2018-03-08x86: fold FMA and FMA4 templatesJan Beulich1-1536/+264
2018-03-08x86: drop {X,Y,Z}MMWORD_MNEM_SUFFIXJan Beulich1-1/+1
2018-03-08x86: drop bogus NoAVXJan Beulich1-7/+7
2018-03-08x86: avoid SSE check for LDMXCSR/STMXCSRJan Beulich1-2/+2
2018-03-08x86: drop FloatDJan Beulich1-19724/+19724
2018-03-08x86: bogus VMOVD with 64-bit operands should only allow for registersJan Beulich1-4/+4
2018-03-08x86: fold AVX vcvtpd2ps memory formsJan Beulich1-18/+1
2018-03-01x86: Encode AVX256/AVX512 vpsub[bwdq] with VEX128/EVEX128H.J. Lu1-12/+12
2018-02-27x86: Add -O[2|s] assembler command-line optionsH.J. Lu1-5322/+5336
2018-02-22x86: Add {rex} pseudo prefixH.J. Lu1-0/+14
2018-01-23Enable Intel PCONFIG instruction.Igor Tsimbalist1-5280/+5294
2018-01-23Enable Intel WBNOINVD instruction.Igor Tsimbalist1-5279/+5293
2018-01-17Replace CET bit with IBT and SHSTK bits.Igor Tsimbalist1-5332/+5332
2018-01-11Remove VL variants for 4FMAPS and 4VNNIW insns.Igor Tsimbalist1-160/+0
2018-01-10x86: fix Disp8 handling for scalar AVX512_4FMAPS insnsJan Beulich1-2/+2
2018-01-10x86: fix Disp8 handling for AVX512VL VPCMP*{B,W} variantsJan Beulich1-48/+48
2018-01-08x86: Properly encode vmovd with 64-bit memeoryH.J. Lu1-38/+4
2018-01-03Update year range in copyright notice of binutils filesAlan Modra1-1/+1
2017-12-18x86: fold certain AVX and AVX2 templatesJan Beulich1-3773/+586
2017-12-18x86: fold RegXMM/RegYMM/RegZMM into RegSIMDJan Beulich1-46173/+46173
2017-12-18x86: drop FloatReg and FloatAccJan Beulich1-32462/+32462
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