aboutsummaryrefslogtreecommitdiff
path: root/opcodes/ChangeLog
AgeCommit message (Expand)AuthorFilesLines
2017-03-09Update -maltivec and -mvsx options to only enable their oldest instructions.binutils-2_27-branchPeter Bergner1-0/+5
2017-03-08Add support for the new 'lnia' extended mnemonic.Peter Bergner1-0/+6
2017-02-28Backport addition of scv and rfscv P9 instructions.Peter Bergner1-0/+7
2016-09-16Backport lastest POWER9 support to match final ISA 3.0 documentation.Peter Bergner1-0/+19
2016-08-03Bump to 2.27.0Tristan Gingold1-0/+4
2016-08-03Release 2.27binutils-2_27Tristan Gingold1-0/+4
2016-07-01Bump version to 2.26.90 (on branch 2.27)Tristan Gingold1-0/+4
2016-07-01Bump version to 2.27.51Tristan Gingold1-0/+4
2016-07-01x86: allow suffix-less movzw and 64-bit movzbJan Beulich1-0/+7
2016-07-01x86: remove stray instruction attributesJan Beulich1-0/+15
2016-07-01x86/Intel: fix operand checking for MOVSDJan Beulich1-0/+5
2016-06-30Fix typo in commentYao Qi1-0/+4
2016-06-28[AArch64] Make register indices be full 64-bit valuesRichard Sandiford1-0/+7
2016-06-25remove a few sentinalsTrevor Saunders1-0/+5
2016-06-23[ARC] Misc minor edits/fixesGraham Markall1-0/+5
2016-06-22Add support for yet some more new ISA 3.0 instructions.Peter Bergner1-0/+10
2016-06-22addmore extern CTrevor Saunders1-0/+4
2016-06-21Arc assembler: Convert nps400 from a machine type to an extension.Graham Markall1-0/+10
2016-06-17opcodes,gas: sparc: fix rdasr,wrasr,rdpr,wrpr,rdhpr,wrhpr insns.Jose E. Marchesi1-0/+16
2016-06-17opcodes,gas: adjust sparc insns and make GAS aware of itJose E. Marchesi1-0/+5
2016-06-17bfd,opcodes: sparc: new opcode v9{c,d,e,v,m} architectures and bfd machine nu...Jose E. Marchesi1-0/+25
2016-06-15Fix simple gas testsuite failures.Nick Clifton1-0/+6
2016-06-15opcodes/arc: Fix extract for some add_s instructionsAndrew Burgess1-0/+4
2016-06-14opcode/gas: Fix incorrect dates on ChangeLog entriesGraham Markall1-3/+3
2016-06-14[ARC] Add ldbit for npsGraham Markall1-0/+5
2016-06-14[ARC] Add deep packet inspection instructions for npsGraham Markall1-0/+6
2016-06-14[ARC] Add arithmetic and logic instructions for npsGraham Markall1-0/+25
2016-06-10S/390: Dump unknown instructions according to their length.Andreas Krebbel1-0/+10
2016-06-09Print symbol names in comments for LDS/STS disassembly.Denis Chertykov1-0/+5
2016-06-07PowerPC VLEAlan Modra1-0/+11
2016-06-07[ARM] Add command line option for RAS extension.Matthew Wahab1-0/+5
2016-06-03Re-add support for lbarx, lharx, stbcx. and sthcx. insns back to the E6500 cpu.Peter Bergner1-0/+6
2016-06-03Handle indirect branches for AMD64 and Intel64H.J. Lu1-0/+14
2016-06-02Add support for 48 and 64 bit ARC instructions.Andrew Burgess1-0/+33
2016-06-01add more extern CTrevor Saunders1-0/+5
2016-06-01Add support for some variants of the ARC nps400 rflt instruction.Graham Markall1-0/+5
2016-05-31sh: make constant unsigned to avoid narrowingTrevor Saunders1-0/+5
2016-05-29Add missing ChangeLog entriesH.J. Lu1-0/+10
2016-05-27Update x86 CPU_XXX_FLAGS handlingH.J. Lu1-0/+32
2016-05-27Replace CpuAMD64/CpuIntel64 with AMD64/Intel64H.J. Lu1-0/+18
2016-05-27Correct CpuMax in i386-opc.hH.J. Lu1-0/+7
2016-05-27Improve the MSP430 disassembler's handling of memory read errors.Nick Clifton1-0/+14
2016-05-26Add support for new POWER ISA 3.0 instructions.Peter Bergner1-0/+5
2016-05-25Enable VREX for all AVX512 directivesH.J. Lu1-0/+9
2016-05-25Enable VREX for AVX512 directivesH.J. Lu1-0/+7
2016-05-25Reimplement .no87/.nommx/.nosse/.noavx directivesH.J. Lu1-0/+6
2016-05-23[ARC] Update instruction type and delay slot info.Claudiu Zissulescu1-0/+12
2016-05-23[ARC] Add XY registers, update neg instruction.Claudiu Zissulescu1-0/+4
2016-05-23[ARC] Rename "class" named attributes.Claudiu Zissulescu1-0/+6
2016-05-23tic54x: rename typedef of struct symbol_Trevor Saunders1-0/+5
generated by cgit v1.1 at 2024-08-05 06:02:51 +0000