| Age | Commit message (Expand) | Author | Files | Lines |
|---|
| 2023-11-16 | aarch64: Add support for VMSA feature enhancements. | Srinath Parvathaneni | 1 | -1/+20 |
| 2023-11-16 | aarch64: Add new AT system instructions. | Srinath Parvathaneni | 1 | -1/+4 |
| 2023-11-16 | aarch64: Add support to new features in RAS extension. | Srinath Parvathaneni | 1 | -1/+13 |
| 2023-11-16 | aarch64: Add features to the Statistical Profiling Extension. | Srinath Parvathaneni | 1 | -1/+10 |
| 2023-11-10 | Add support for ilp32 register alias. | Lulu Cai | 1 | -4/+4 |
| 2023-11-07 | aarch64: Add arch support for LSE128 extension | Victor Do Nascimento | 1 | -0/+3 |
| 2023-11-07 | aarch64: Add LSE128 instruction operand support | Victor Do Nascimento | 1 | -0/+2 |
| 2023-11-07 | aarch64: Add THE system register support | Victor Do Nascimento | 1 | -0/+2 |
| 2023-11-07 | RISC-V: Add support for XCValu extension in CV32E40P | Mary Bennett | 2 | -0/+72 |
| 2023-11-07 | RISC-V: Add support for XCVmac extension in CV32E40P | Mary Bennett | 2 | -0/+44 |
| 2023-11-03 | RISC-V: reduce redundancy in load/store macro insn handling | Jan Beulich | 1 | -19/+3 |
| 2023-11-02 | aarch64: Add support for GCSB DSYNC instruction. | Srinath Parvathaneni | 1 | -0/+2 |
| 2023-11-02 | aarch64: Add support for GCS extension. | srinath | 1 | -1/+3 |
| 2023-11-02 | aarch64: Add support for Check Feature Status Extension. | Srinath Parvathaneni | 1 | -2/+5 |
| 2023-11-02 | aarch64: Add support for Armv8.9-A and Armv9.4-A Architectures. | srinath | 1 | -1/+8 |
| 2023-10-19 | RISC-V: Remove semicolons from DECLARE_INSN | Tsukasa OI | 1 | -15/+15 |
| 2023-10-17 | RISC-V: Fix typo | Tsukasa OI | 1 | -1/+1 |
| 2023-10-10 | LoongArch/GAS: Add support for branch relaxation | mengqinggang | 1 | -0/+12 |
| 2023-10-08 | as: add option for generate R_LARCH_32/64_PCREL. | cailulu | 1 | -0/+1 |
| 2023-10-04 | aarch64: system register aliasing detection | Victor Do Nascimento | 1 | -0/+1 |
| 2023-09-26 | aarch64: Allow feature flags to occupy >64 bits | Richard Sandiford | 1 | -23/+39 |
| 2023-09-26 | aarch64: Restructure feature flag handling | Richard Sandiford | 1 | -151/+268 |
| 2023-09-25 | Revert "arc: Update opcode related include files for ARCv3." | Claudiu Zissulescu | 3 | -257/+56 |
| 2023-09-25 | arc: Update opcode related include files for ARCv3. | Claudiu Zissulescu | 3 | -56/+257 |
| 2023-09-05 | RISC-V: fold duplicate code in vector_macro() | Jan Beulich | 1 | -1/+0 |
| 2023-09-05 | RISC-V: Add 'Smcntrpmf' extension and its CSRs | Tsukasa OI | 1 | -4/+12 |
| 2023-08-22 | aarch64: Improve naming conventions for A and R-profile architecture | Victor Do Nascimento | 1 | -54/+54 |
| 2023-08-21 | bpf: correct neg and neg32 instruction encoding | David Faust | 1 | -2/+2 |
| 2023-08-16 | kvx: New port. | Paul Iannetta | 1 | -0/+3159 |
| 2023-08-15 | RISC-V: Make "fli.h" available to 'Zvfh' + 'Zfa' | Tsukasa OI | 1 | -0/+1 |
| 2023-08-15 | RISC-V: Add support for the 'Zihintntl' extension | Tsukasa OI | 2 | -0/+28 |
| 2023-08-15 | RISC-V: remove indirection from register tables | Jan Beulich | 1 | -7/+9 |
| 2023-08-02 | Revert "2.41 Release sources" | Sam James | 2 | -2/+52 |
| 2023-08-02 | 2.41 Release sourcesbinutils-2_41-release | Nick Clifton | 2 | -52/+2 |
| 2023-07-30 | bpf: include, bfd, opcodes: add EF_BPF_CPUVER ELF header flags | Jose E. Marchesi | 1 | -1/+1 |
| 2023-07-25 | bpf: Add atomic compare-and-exchange instructions | David Faust | 1 | -1/+5 |
| 2023-07-24 | bpf: gas,include,opcode: add suppor for instructions BSWAP{16,32,64} | Jose E. Marchesi | 1 | -0/+6 |
| 2023-07-24 | bpf: add support for jal/gotol jump instruction with 32-bit target | Jose E. Marchesi | 1 | -1/+2 |
| 2023-07-21 | bpf: opcodes, gas: support for signed load V4 instructions | Jose E. Marchesi | 1 | -0/+3 |
| 2023-07-21 | bpf: opcodes, gas: support for signed register move V4 instructions | Jose E. Marchesi | 1 | -0/+5 |
| 2023-07-21 | DesCGENization of the BPF binutils port | Jose E. Marchesi | 1 | -0/+306 |
| 2023-07-18 | RISC-V: Supports Zcb extension. | Jiawei | 2 | -0/+52 |
| 2023-07-03 | RISC-V: Zvkh[a,b]: Remove individual instruction class | Christoph Müllner | 1 | -2/+0 |
| 2023-07-01 | RISC-V: Add support for the Zvksh ISA extension | Christoph Müllner | 2 | -0/+9 |
| 2023-07-01 | RISC-V: Add support for the Zvksed ISA extension | Christoph Müllner | 2 | -0/+12 |
| 2023-07-01 | RISC-V: Add support for the Zvknh[a,b] ISA extensions | Christoph Müllner | 2 | -0/+14 |
| 2023-07-01 | RISC-V: Add support for the Zvkned ISA extension | Christoph Müllner | 2 | -0/+36 |
| 2023-07-01 | RISC-V: Add support for the Zvkg ISA extension | Christoph Müllner | 2 | -0/+9 |
| 2023-07-01 | RISC-V: Add support for the Zvbc extension | Nathan Huckleberry | 2 | -0/+15 |
| 2023-07-01 | RISC-V: Add support for the Zvbb ISA extension | Christoph Müllner | 2 | -0/+55 |
