| Age | Commit message (Expand) | Author | Files | Lines |
|---|
| 2021-03-16 | RISC-V : Support bitmanip-0.93 ZBA/ZBB/ZBC instructions | Kuan-Lin Chen | 1 | -0/+104 |
| 2021-02-05 | RISC-V: PR27348, Remove obsolete Xcustom support. | Nelson Chu | 1 | -72/+0 |
| 2021-02-04 | RISC-V: Removed the v0.93 bitmanip ZBA/ZBB/ZBC instructions. | Nelson Chu | 1 | -108/+0 |
| 2021-01-15 | RISC-V: Comments tidy and improvement. | Nelson Chu | 1 | -8/+8 |
| 2021-01-07 | RISC-V: Add pause hint instruction. | Philipp Tomsich | 1 | -0/+3 |
| 2021-01-07 | RISC-V: Support riscv bitmanip frozen ZBA/ZBB/ZBC instructions (v0.93). | Claire Xenia Wolf | 1 | -0/+108 |
| 2021-01-01 | Update year range in copyright notice of binutils files | Alan Modra | 1 | -1/+1 |
| 2020-06-30 | RISC-V: Support debug and float CSR as the unprivileged ones. | Nelson Chu | 1 | -24/+42 |
| 2020-06-30 | RISC-V: Cleanup the include/opcode/riscv-opc.h. | Nelson Chu | 1 | -33/+26 |
| 2020-06-12 | RISC-V: Drop the privileged spec v1.9 support. | Nelson Chu | 1 | -218/+217 |
| 2020-05-20 | [PATCH v2 0/9] RISC-V: Support version controling for ISA standard extensions... | Nelson Chu | 1 | -261/+248 |
| 2020-03-30 | RISC-V: Update CSR to privileged spec 1.11. | Nelson Chu | 1 | -6/+19 |
| 2020-02-20 | RISC-V: Support the ISA-dependent CSR checking. | Nelson Chu | 1 | -244/+244 |
| 2018-10-02 | RISC-V: Add fence.tso instruction | Palmer Dabbelt | 1 | -0/+2 |
| 2018-05-08 | RISC-V: Add missing hint instructions from RV128I. | Jim Wilson | 1 | -0/+6 |
| 2018-01-04 | RISC-V: Add 2 missing privileged registers. | Jim Wilson | 1 | -4/+8 |
| 2017-12-28 | RISC-V: Add missing privileged spec registers. | Jim Wilson | 1 | -148/+208 |
| 2017-11-07 | RISC-V: Add satp as an alias for sptbr | Palmer Dabbelt | 1 | -2/+5 |
| 2017-03-31 | RISC-V: Add physical memory protection CSRs | Andrew Waterman | 1 | -0/+40 |
| 2017-02-24 | Add new counter-enable CSRs | Andrew Waterman | 1 | -0/+4 |
| 2017-02-15 | Add SFENCE.VMA instruction | Andrew Waterman | 1 | -0/+3 |
| 2017-01-03 | Add support for the Q extension to the RISCV ISA. | Kito Cheng | 1 | -0/+102 |
| 2016-11-01 | Add support for RISC-V architecture. | Nick Clifton | 1 | -0/+1160 |
