aboutsummaryrefslogtreecommitdiff
path: root/gas/testsuite
AgeCommit message (Expand)AuthorFilesLines
2020-05-05Restore readelf's warnings that describe real problems with the file being ex...Nick Clifton1-2/+2
2020-05-04gas: PR 25863: Fix scalar vmul inside it block when assembling for MVEAndre Simoes Dias Vieira2-0/+16
2020-05-04Fix an illegal memory access in the assembler when generating a DWARF5 file/d...Nick Clifton3-0/+14
2020-04-30AArch64: add GAS support for UDF instructionAlex Coplan5-0/+27
2020-04-29Update expected disassembly after recent update.Nick Clifton1-1/+1
2020-04-29Fix the disassmbly of SH instructions which have an unsigned 8-bit immediate ...Nick Clifton2-0/+4
2020-04-27x86: Add i386 PE big-object supportTamar Christina2-3/+2
2020-04-26Improve -mlfence-after-loadliuhongt18-4/+455
2020-04-22xtensa: fix PR ld/25861Max Filippov1-1/+1
2020-04-22.symver fixesAlan Modra3-8/+3
2020-04-21symver11.s: Add ".balign 8"H.J. Lu1-0/+1
2020-04-21Disallow PC relative for CMPI on MC68000/10Andreas Schwab3-0/+33
2020-04-21BFD: Exclude sections with no content from compress check.Tamar Christina2-0/+19
2020-04-21gas: Extend .symver directiveH.J. Lu24-8/+172
2020-04-20[AArch64, Binutils] Add missing TSB instructionSudakshina Das3-7/+15
2020-04-20[AArch64, Binutils] Make hint space instructions valid for Armv8-aSudakshina Das5-16/+1
2020-04-16Stop the MIPS assembler from accepting ifunc symbols.Nick Clifton2-3/+4
2020-04-16cpu,gas,opcodes: support for eBPF JMP32 instruction classDavid Faust3-0/+57
2020-04-07Add support for intel TSXLDTRK instructions$Cui,Lili4-0/+34
2020-04-02Add support for intel SERIALIZE instructionLiliCui4-0/+31
2020-04-02ld: Disable ifunc tests on SolarisRainer Orth4-4/+4
2020-04-01x86: Force relocation against local absolute symbolH.J. Lu5-3/+13
2020-04-01gas: Fix some x86_64 testcases for Solaris not using R_X86_64_PLT32 [PR25732]Rainer Orth7-47/+77
2020-03-30RISC-V: Update CSR to privileged spec 1.11.Nelson Chu17-384/+426
2020-03-22s12z disassembler tidyAlan Modra1-5/+1
2020-03-17Fix a small set of Z80 problems.Sergey Belyashov13-97/+353
2020-03-13gas, arm: PR25660L Fix vadd/vsub with lt and le condition codes for MVEAndre Vieira6-0/+88
2020-03-11i386: Add tests for lfence with load/indirect branch/retH.J. Lu26-0/+711
2020-03-11Add support for generating DWARF-5 format directory and file name tables from...Nick Clifton3-14/+33
2020-03-09x86: use template for AVX/AVX512 floating point comparison insnsJan Beulich4-0/+448
2020-03-07Re: Add support for a ".file 0" directive if supporting DWARF 5 or higher.Alan Modra1-9/+8
2020-03-06Add support for a ".file 0" directive if supporting DWARF 5 or higher.Nick Clifton3-0/+25
2020-03-06x86: replace NoRex64 on VEX-encoded insnsJan Beulich6-50/+50
2020-03-06x86: correct MPX insn w/o base or index encoding in 16-bit modeJan Beulich3-0/+159
2020-03-06x86: add missing IgnoreSizeJan Beulich30-22/+253
2020-03-06x86: refine TPAUSE and UMWAITJan Beulich6-12/+51
2020-03-04RISC-V: Support assembler modifier %got_pcrel_hi.Nelson Chu4-7/+18
2020-03-04Generate a warning in the ARM assembler if a PC-relative thumb load instructi...Alexandre Oliva5-6/+8
2020-03-04x86: support VMGEXITJan Beulich4-3/+7
2020-03-03The patch fixed invalid compilation of instruction LD IY,(HL) and disassemble...Sergey Belyashov4-2/+42
2020-03-03x86: Allow integer conversion without suffix in AT&T syntaxH.J. Lu7-24/+48
2020-03-03x86: Improve -malign-branchHongtao Liu5-0/+243
2020-02-26[binutils][arm] Arm CDE CX*A instructions allow condition codeMatthew Malcomson3-22/+34
2020-02-20RISC-V: Support the read-only CSR checking.Nelson Chu6-0/+459
2020-02-20RISC-V: Disable the CSR checking by default.Nelson Chu2-2/+2
2020-02-20RISC-V: Support the ISA-dependent CSR checking.Nelson Chu6-2/+78
2020-02-19RISC-V: Convert the ADD/ADDI to the compressed MV/LI if RS1 is zero.Jim Wilson2-0/+14
2020-02-19Various fixes for the Z80 support.Sergey Belyashov21-23/+24
2020-02-19x86: Mark cvtpi2ps and cvtpi2pd as MMXH.J. Lu4-0/+23
2020-02-17x86/Intel: don't swap operands of MONITOR{,X} and MWAIT{,X}Jan Beulich7-0/+105
generated by cgit v1.1 at 2025-02-10 14:13:10 +0000