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AgeCommit message (Expand)AuthorFilesLines
2022-12-14RISC-V: Add string length check for operands in ASLi Xu1-1/+2
2022-12-14x86: adjust type checking constructsJan Beulich1-2/+2
2022-12-12x86: further re-work insn/suffix recognition to also cover MOVSXJan Beulich1-1/+5
2022-12-12x86: drop (now) stray IsStringJan Beulich1-9/+7
2022-12-12x86: move bad-use-of-TLS-reloc checkJan Beulich1-32/+35
2022-12-12x86-64: allow HLE store of accumulator to absolute 32-bit addressJan Beulich1-5/+2
2022-12-12ix86: don't recognize/derive Q suffix in the common caseJan Beulich2-25/+81
2022-12-12x86: re-work insn/suffix recognitionJan Beulich2-159/+169
2022-12-12x86: constify parse_insn()'s inputJan Beulich1-7/+8
2022-12-12x86: generate template sets data at build timeJan Beulich1-15/+10
2022-12-12x86: drop sentinel from i386_optab[]Jan Beulich1-22/+11
2022-12-12x86: instantiate i386_{op,reg}tab[] in gas instead of in libopcodesJan Beulich1-0/+2
2022-12-02x86: drop most OPERAND_TYPE_* (and rework the rest)Jan Beulich1-47/+81
2022-12-02x86: simplify and slightly correct XCHG vs NOP checkingJan Beulich1-5/+3
2022-12-02x86: also use D for XCHG and TESTJan Beulich1-4/+8
2022-12-01x86: rework of match_template()'s suffix checkingJan Beulich1-27/+5
2022-12-01x86: drop No_ldSufJan Beulich1-2/+0
2022-12-01x86/Intel: drop LONG_DOUBLE_MNEM_SUFFIXJan Beulich2-24/+24
2022-12-01x86/Intel: restrict use of LONG_DOUBLE_MNEM_SUFFIXJan Beulich1-7/+7
2022-11-30x86/Intel: adjustment to restricted suffix derivationJan Beulich1-3/+8
2022-11-30x86: clean up after removal of support for gcc <= 2.8.1Jan Beulich1-14/+17
2022-11-30x86: drop FloatRJan Beulich1-4/+8
2022-11-28xtensa: allow dynamic configurationMax Filippov3-20/+3
2022-11-28RISC-V: Better support for long instructions (assembler)Tsukasa OI1-9/+32
2022-11-25riscv: Add AIA extension support (Smaia, Ssaia)Christoph Müllner1-0/+22
2022-11-24x86: widen applicability and use of CheckRegSizeJan Beulich1-9/+5
2022-11-24x86: correct handling of LAR and LSLJan Beulich1-1/+3
2022-11-19RISC-V: Add 'Ssstateen' extension and its CSRsTsukasa OI1-8/+12
2022-11-18GAS fix alignment for aarch64-peZac Walker1-0/+3
2022-11-17[gas, aarch64]: fix build breakage for aarch64-peIndu Bhagat1-19/+22
2022-11-17i386: Move i386_seg_prefixes to gasH.J. Lu1-0/+10
2022-11-15gas: generate .sframe from CFI directivesIndu Bhagat5-0/+164
2022-11-16aarch64-pe can't fill 16 bytes in section .textAlan Modra1-2/+6
2022-11-15Add AMD znver4 processor supportTejas Joshi1-3/+6
2022-11-14aarch64: Add support for Common Short Sequence Compression extensionAndre Vieira1-0/+4
2022-11-14x86: fold special-operand insn attributes into a single enumJan Beulich1-12/+12
2022-11-14[gas] arm: Add support for new unwinder directive ".pacspval".Srinath Parvathaneni1-0/+17
2022-11-14arm: Add support for Cortex-X1C CPU.Srinath Parvathaneni1-0/+3
2022-11-11x86: drop stray IsString from PadLock insnsJan Beulich1-1/+0
2022-11-11x86: drop duplicate sse4a entry from cpu_arch[]Jan Beulich1-1/+0
2022-11-10i386: Check invalid (%dx) usageH.J. Lu1-0/+16
2022-11-09x86/Intel: don't accept malformed EXTRQ / INSERTQJan Beulich1-1/+2
2022-11-08Support Intel RAO-INTKong Lingling1-0/+1
2022-11-04Support Intel AVX-NE-CONVERTkonglin11-0/+1
2022-11-02x86: simplify expressions in update_imm()Jan Beulich1-23/+14
2022-11-02RISC-V: Fixed the missing $x+arch when adding odd paddings for alignment.Nelson Chu1-29/+36
2022-11-02Support Intel MSRLISTHu, Lin11-0/+1
2022-11-02Support Intel WRMSRNSHu, Lin11-0/+1
2022-11-02Add handler for more i386_cpu_flagsKong Lingling1-0/+17
2022-11-02Support Intel CMPccXADDHaochen Jiang1-1/+2
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