| Age | Commit message (Expand) | Author | Files | Lines |
|---|
| 2022-09-21 | RISC-V: Implement Ztso extension | Shihua | 1 | -0/+1 |
| 2022-09-16 | RISC-V: Make g imply zmmul extension. | Nelson Chu | 1 | -1/+1 |
| 2022-08-30 | RISC-V: Add 'Zmmul' extension in assembler. | Tsukasa OI | 1 | -0/+6 |
| 2022-08-10 | RISC-V: Remove R_RISCV_GNU_VTINHERIT/R_RISCV_GNU_VTENTRY | Fangrui Song | 1 | -29/+3 |
| 2022-07-07 | RISC-V: Added Zfhmin and Zhinxmin. | Tsukasa OI | 1 | -45/+52 |
| 2022-07-07 | RISC-V: Fix requirement handling on Zhinx+{D,Q} | Tsukasa OI | 1 | -5/+25 |
| 2022-07-04 | RISC-V: Update Zihintpause extension version | Tsukasa OI | 1 | -1/+1 |
| 2022-06-28 | RISC-V: Add 'Sstc' extension and its CSRs | Tsukasa OI | 1 | -0/+1 |
| 2022-06-28 | RISC-V: Add 'Sscofpmf' extension with its CSRs | Tsukasa OI | 1 | -0/+1 |
| 2022-06-28 | RISC-V: Add 'Smstateen' extension and its CSRs | Tsukasa OI | 1 | -0/+1 |
| 2022-06-22 | RISC-V: Reorder the prefixed extensions which are out of order. | Nelson Chu | 1 | -23/+0 |
| 2022-06-22 | RISC-V: Use single h extension to control hypervisor CSRs and instructions. | Nelson Chu | 1 | -11/+5 |
| 2022-06-22 | RISC-V: Add 'H' to canonical extension ordering | Tsukasa OI | 1 | -1/+1 |
| 2022-06-22 | RISC-V: Prepare i18n for required ISA extensions | Tsukasa OI | 1 | -13/+14 |
| 2022-06-08 | Revert reloc howto nits | Alan Modra | 1 | -1/+1 |
| 2022-06-08 | HOWTO size encoding | Alan Modra | 1 | -55/+55 |
| 2022-05-30 | RISC-V: Add zhinx extension supports. | jiawei | 1 | -4/+20 |
| 2022-05-25 | RISC-V: Fix RV32Q conflict | Tsukasa OI | 1 | -2/+3 |
| 2022-05-20 | RISC-V: Update zfinx implement with zicsr. | Jia-Wei Chen | 1 | -0/+1 |
| 2022-05-19 | RISC-V: Fix canonical extension order (K and J) | Tsukasa OI | 1 | -1/+1 |
| 2022-05-17 | RISC-V: Added half-precision floating-point v1.0 instructions. | Nelson Chu | 1 | -0/+11 |
| 2022-03-18 | RISC-V: Cache management instructions | Tsukasa OI | 1 | -0/+6 |
| 2022-03-18 | RISC-V: Prefetch hint instructions and operand set | Tsukasa OI | 1 | -0/+3 |
| 2022-02-25 | RISC-V: Remove a loop in the ISA parser | Tsukasa OI | 1 | -7/+4 |
| 2022-02-23 | RISC-V: PR28733, add missing extension info to 'unrecognized opcode' error | Patrick O'Neill | 1 | -0/+94 |
| 2022-02-22 | RISC-V: Maintain a string to hold the canonical order | Kito Cheng | 1 | -17/+5 |
| 2022-01-07 | RISC-V: Updated the default ISA spec to 20191213. | Nelson Chu | 1 | -1/+3 |
| 2022-01-02 | Update year range in copyright notice of binutils files | Alan Modra | 1 | -1/+1 |
| 2021-12-16 | RISC-V: Support svinval extension with frozen version 1.0. | Nelson Chu | 1 | -0/+3 |
| 2021-12-09 | RISC-V: Clarify the behavior of .option arch directive. | Nelson Chu | 1 | -24/+15 |
| 2021-11-22 | RISC-V: Removed the redundant NULL pointer check in the riscv_update_subset. | Nelson Chu | 1 | -3/+0 |
| 2021-11-22 | RISC-V: PR28610, Fix ASAN heap-buffer-overflow error in riscv_update_subset. | Nelson Chu | 1 | -7/+12 |
| 2021-11-19 | RISC-V: Support new .option arch directive. | Nelson Chu | 1 | -24/+134 |
| 2021-11-18 | RISC-V: Add instructions and operand set for z[fdq]inx | jiawei | 1 | -0/+9 |
| 2021-11-18 | RISC-V: Add mininal support for z[fdq]inx | jiawei | 1 | -0/+12 |
| 2021-11-17 | RISC-V: Support rvv extension with released version 1.0. | Nelson Chu | 1 | -1/+75 |
| 2021-11-16 | RISC-V: Scalar crypto instructions and operand set. | jiawei | 1 | -0/+25 |
| 2021-11-16 | RISC-V: Minimal support of scalar crypto extension. | jiawei | 1 | -1/+29 |
| 2021-11-11 | RISC-V: Dump objects according to the elf architecture attribute. | Nelson Chu | 1 | -3/+66 |
| 2021-11-04 | RISC-V: Clarify the behavior of .option rvc or norvc. | Nelson Chu | 1 | -0/+65 |
| 2021-10-07 | RISC-V: Add support for Zbs instructions | Philipp Tomsich | 1 | -0/+1 |
| 2021-10-07 | RISC-V: Update extension version for Zb[abc] to 1.0.0 | Philipp Tomsich | 1 | -3/+3 |
| 2021-09-28 | RISC-V: Fix wrong version number when arch contains 'p'. | Cooper Qu | 1 | -6/+2 |
| 2021-09-28 | RISC-V: Allow to add numbers in the prefixed extension names. | Nelson Chu | 1 | -38/+44 |
| 2021-09-17 | RISC-V: Merged extension string tables and their version tables into one. | Nelson Chu | 1 | -127/+223 |
| 2021-09-07 | Fix illegal memory access triggered by an attempt to disassemble a corrupt RI... | Nick Clifton | 1 | -0/+7 |
| 2021-07-20 | RISC-V: Minor updates for architecture parser. | Nelson Chu | 1 | -94/+82 |
| 2021-05-26 | RISC-V: Allow to link the objects with unknown prefixed extensions. | Nelson Chu | 1 | -1/+2 |
| 2021-05-13 | RISC-V: Record implicit subsets in a table, to avoid repeated codes. | Nelson Chu | 1 | -54/+49 |
| 2021-04-13 | RISC-V: Don't report the mismatched version warning for the implicit extensions. | Nelson Chu | 1 | -8/+3 |
