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Diffstat (limited to 'sim/testsuite/frv/sdivi.cgs')
| -rw-r--r-- | sim/testsuite/frv/sdivi.cgs | 74 |
1 files changed, 74 insertions, 0 deletions
diff --git a/sim/testsuite/frv/sdivi.cgs b/sim/testsuite/frv/sdivi.cgs new file mode 100644 index 0000000..eb781e7 --- /dev/null +++ b/sim/testsuite/frv/sdivi.cgs @@ -0,0 +1,74 @@ +# frv testcase for sdivi $GRi,$s12,$GRk +# mach: all + + .include "testutils.inc" + + start + + .global sdivi +sdivi: + ; simple division 12 / 3 + set_gr_immed 12,gr1 + sdivi gr1,3,gr2 + test_gr_immed 4,gr2 + + ; Random example + set_gr_limmed 0xfedc,0xba98,gr1 + sdivi gr1,0x7ff,gr2 + test_gr_limmed 0xffff,0xdb93,gr2 + + ; Random negative example + set_gr_limmed 0xfedc,0xba98,gr1 + sdivi gr1,-2048,gr2 + test_gr_immed 0x2468,gr2 + + ; Special case from the Arch Spec Vol 2 + or_spr_immed 0x20,isr ; turn on isr.edem + set_gr_limmed 0x8000,0x0000,gr1 + sdivi gr1,-1,gr2 + test_gr_limmed 0x7fff,0xffff,gr2 + test_spr_bits 0x4,2,1,isr ; isr.aexc is set + + and_spr_immed -33,isr ; turn off isr.edem + ; set up exception handler + set_psr_et 1 + and_spr_immed -4081,tbr ; clear tbr.tt + set_gr_spr tbr,gr17 + inc_gr_immed 0x170,gr17 ; address of exception handler + set_bctrlr_0_0 gr17 + set_spr_immed 128,lcr + set_gr_immed 0,gr15 + + ; divide will cause overflow + set_spr_addr ok1,lr + set_gr_addr e1,gr17 + set_gr_limmed 0x8000,0x0000,gr1 +e1: sdivi gr1,-1,gr2 + test_gr_immed 1,gr15 + test_gr_limmed 0x8000,0x0000,gr2 + + ; divide by zero + set_spr_addr ok2,lr + set_gr_addr e2,gr17 +e2: sdivi gr1,0,gr2 ; divide by zero + test_gr_immed 2,gr15 + + pass + +ok1: ; exception handler for overflow + test_spr_bits 0x18,3,0x2,isr ; isr.dtt is set + test_spr_gr epcr0,gr17 ; return address set + test_spr_bits 0x0001,0,0x1,esr0 ; esr0 is valid + test_spr_bits 0x003e,1,0x13,esr0 ; esr0.ec is set + inc_gr_immed 1,gr15 + rett 0 + fail + +ok2: ; exception handler for divide by zero + test_spr_bits 0x18,3,0x3,isr ; isr.dtt is set + test_spr_gr epcr0,gr17 ; return address set + test_spr_bits 0x0001,0,0x1,esr0 ; esr0 is valid + test_spr_bits 0x003e,1,0x13,esr0 ; esr0.ec is set + inc_gr_immed 1,gr15 + rett 0 + fail |