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-rw-r--r--sim/testsuite/frv/ccmp.cgs134
1 files changed, 134 insertions, 0 deletions
diff --git a/sim/testsuite/frv/ccmp.cgs b/sim/testsuite/frv/ccmp.cgs
new file mode 100644
index 0000000..52d5310
--- /dev/null
+++ b/sim/testsuite/frv/ccmp.cgs
@@ -0,0 +1,134 @@
+# frv testcase for ccmp $GRi,$GRj,$CCi,$cond
+# mach: all
+
+ .include "testutils.inc"
+
+ start
+
+ .global ccmp
+ccmp:
+ set_spr_immed 0x1b1b,cccr
+
+ set_gr_immed 1,gr7
+ set_gr_immed 2,gr8
+ set_icc 0x0f,0 ; Set mask opposite of expected
+ ccmp gr8,gr7,cc0,1
+ test_icc 0 0 0 0 icc0
+
+ set_gr_immed 1,gr7
+ set_gr_limmed 0x8000,0x0000,gr8
+ set_icc 0x0d,0 ; Set mask opposite of expected
+ ccmp gr8,gr7,cc0,1
+ test_icc 0 0 1 0 icc0
+
+ set_icc 0x0b,0 ; Set mask opposite of expected
+ ccmp gr8,gr8,cc4,1
+ test_icc 0 1 0 0 icc0
+
+ set_gr_immed 0,gr8
+ set_icc 0x06,0 ; Set mask opposite of expected
+ ccmp gr8,gr7,cc4,1
+ test_icc 1 0 0 1 icc0
+
+ set_gr_immed 1,gr7
+ set_gr_immed 2,gr8
+ set_icc 0x0f,0 ; Set mask opposite of expected
+ ccmp gr8,gr7,cc0,0
+ test_icc 1 1 1 1 icc0
+
+ set_gr_immed 1,gr7
+ set_gr_limmed 0x8000,0x0000,gr8
+ set_icc 0x0d,0 ; Set mask opposite of expected
+ ccmp gr8,gr7,cc0,0
+ test_icc 1 1 0 1 icc0
+
+ set_icc 0x0b,0 ; Set mask opposite of expected
+ ccmp gr8,gr8,cc4,0
+ test_icc 1 0 1 1 icc0
+
+ set_icc 0x06,0 ; Set mask opposite of expected
+ ccmp gr8,gr7,cc4,0
+ test_icc 0 1 1 0 icc0
+
+ set_gr_immed 1,gr7
+ set_gr_immed 2,gr8
+ set_icc 0x0f,1 ; Set mask opposite of expected
+ ccmp gr8,gr7,cc1,0
+ test_icc 0 0 0 0 icc1
+
+ set_gr_immed 1,gr7
+ set_gr_limmed 0x8000,0x0000,gr8
+ set_icc 0x0d,1 ; Set mask opposite of expected
+ ccmp gr8,gr7,cc1,0
+ test_icc 0 0 1 0 icc1
+
+ set_icc 0x0b,1 ; Set mask opposite of expected
+ ccmp gr8,gr8,cc5,0
+ test_icc 0 1 0 0 icc1
+
+ set_gr_immed 0,gr8
+ set_icc 0x06,1 ; Set mask opposite of expected
+ ccmp gr8,gr7,cc5,0
+ test_icc 1 0 0 1 icc1
+
+ set_gr_immed 1,gr7
+ set_gr_immed 2,gr8
+ set_icc 0x0f,1 ; Set mask opposite of expected
+ ccmp gr8,gr7,cc1,1
+ test_icc 1 1 1 1 icc1
+
+ set_gr_immed 1,gr7
+ set_gr_limmed 0x8000,0x0000,gr8
+ set_icc 0x0d,1 ; Set mask opposite of expected
+ ccmp gr8,gr7,cc1,1
+ test_icc 1 1 0 1 icc1
+
+ set_icc 0x0b,1 ; Set mask opposite of expected
+ ccmp gr8,gr8,cc5,1
+ test_icc 1 0 1 1 icc1
+
+ set_icc 0x06,1 ; Set mask opposite of expected
+ ccmp gr8,gr7,cc5,1
+ test_icc 0 1 1 0 icc1
+
+ set_gr_immed 1,gr7
+ set_gr_immed 2,gr8
+ set_icc 0x0f,2 ; Set mask opposite of expected
+ ccmp gr8,gr7,cc2,0
+ test_icc 1 1 1 1 icc2
+
+ set_gr_immed 1,gr7
+ set_gr_limmed 0x8000,0x0000,gr8
+ set_icc 0x0d,2 ; Set mask opposite of expected
+ ccmp gr8,gr7,cc2,0
+ test_icc 1 1 0 1 icc2
+
+ set_icc 0x0b,2 ; Set mask opposite of expected
+ ccmp gr8,gr8,cc6,1
+ test_icc 1 0 1 1 icc2
+
+ set_icc 0x06,2 ; Set mask opposite of expected
+ ccmp gr8,gr7,cc6,1
+ test_icc 0 1 1 0 icc2
+
+ set_gr_immed 1,gr7
+ set_gr_immed 2,gr8
+ set_icc 0x0f,3 ; Set mask opposite of expected
+ ccmp gr8,gr7,cc3,0
+ test_icc 1 1 1 1 icc3
+
+ set_gr_immed 1,gr7
+ set_gr_limmed 0x8000,0x0000,gr8
+ set_icc 0x0d,3 ; Set mask opposite of expected
+ ccmp gr8,gr7,cc3,0
+ test_icc 1 1 0 1 icc3
+
+ set_icc 0x0b,3 ; Set mask opposite of expected
+ ccmp gr8,gr8,cc7,1
+ test_icc 1 0 1 1 icc3
+
+ set_icc 0x06,3 ; Set mask opposite of expected
+ ccmp gr8,gr7,cc7,1
+ test_icc 0 1 1 0 icc3
+
+ pass