1 files changed, 126 insertions, 0 deletions
diff --git a/sim/testsuite/frv/candcc.cgs b/sim/testsuite/frv/candcc.cgs
new file mode 100644
index 0000000..c16df73
--- /dev/null
+++ b/sim/testsuite/frv/candcc.cgs
@@ -0,0 +1,126 @@
+# frv testcase for candcc $GRi,$GRj,$GRk,$CCi,$cond
+# mach: all
+
+	.include "testutils.inc"
+
+	start
+
+	.global candcc
+candcc:
+	set_spr_immed	0x1b1b,cccr
+
+	set_gr_limmed  	0xaaaa,0xaaaa,gr7
+	set_gr_limmed  	0x5555,0x5555,gr8
+	set_icc         0x0b,0		; Set mask opposite of expected
+	candcc      	gr7,gr8,gr8,cc0,1
+	test_icc	0 1 1 1 icc0
+	test_gr_immed  	0,gr8
+
+	set_gr_limmed  	0xffff,0x0000,gr8
+	set_icc         0x04,0		; Set mask opposite of expected
+	candcc		gr7,gr8,gr8,cc0,1
+	test_icc	1 0 0 0 icc0
+	test_gr_limmed 	0xaaaa,0x0000,gr8
+
+	set_gr_limmed	0x0000,0xffff,gr8
+	set_icc         0x0d,0		; Set mask opposite of expected
+	candcc		gr7,gr8,gr8,cc4,1
+	test_icc	0 0 0 1 icc0
+	test_gr_limmed	0x0000,0xaaaa,gr8
+
+	set_gr_limmed  	0xaaaa,0xaaaa,gr7
+	set_gr_limmed  	0x5555,0x5555,gr8
+	set_icc         0x0b,0		; Set mask opposite of expected
+	candcc      	gr7,gr8,gr8,cc0,0
+	test_icc	1 0 1 1 icc0
+	test_gr_limmed 	0x5555,0x5555,gr8
+
+	set_gr_limmed  	0xffff,0x0000,gr8
+	set_icc         0x04,0		; Set mask opposite of expected
+	candcc		gr7,gr8,gr8,cc0,0
+	test_icc	0 1 0 0 icc0
+	test_gr_limmed 	0xffff,0x0000,gr8
+
+	set_gr_limmed	0x0000,0xffff,gr8
+	set_icc         0x0d,0		; Set mask opposite of expected
+	candcc		gr7,gr8,gr8,cc4,0
+	test_icc	1 1 0 1 icc0
+	test_gr_limmed	0x0000,0xffff,gr8
+
+	set_gr_limmed  	0xaaaa,0xaaaa,gr7
+	set_gr_limmed  	0x5555,0x5555,gr8
+	set_icc         0x0b,1		; Set mask opposite of expected
+	candcc      	gr7,gr8,gr8,cc1,0
+	test_icc	0 1 1 1 icc1
+	test_gr_immed  	0,gr8
+
+	set_gr_limmed  	0xffff,0x0000,gr8
+	set_icc         0x04,1		; Set mask opposite of expected
+	candcc		gr7,gr8,gr8,cc1,0
+	test_icc	1 0 0 0 icc1
+	test_gr_limmed 	0xaaaa,0x0000,gr8
+
+	set_gr_limmed	0x0000,0xffff,gr8
+	set_icc         0x0d,1		; Set mask opposite of expected
+	candcc		gr7,gr8,gr8,cc5,0
+	test_icc	0 0 0 1 icc1
+	test_gr_limmed	0x0000,0xaaaa,gr8
+
+	set_gr_limmed  	0xaaaa,0xaaaa,gr7
+	set_gr_limmed  	0x5555,0x5555,gr8
+	set_icc         0x0b,1		; Set mask opposite of expected
+	candcc      	gr7,gr8,gr8,cc1,1
+	test_icc	1 0 1 1 icc1
+	test_gr_limmed 	0x5555,0x5555,gr8
+
+	set_gr_limmed  	0xffff,0x0000,gr8
+	set_icc         0x04,1		; Set mask opposite of expected
+	candcc		gr7,gr8,gr8,cc1,1
+	test_icc	0 1 0 0 icc1
+	test_gr_limmed 	0xffff,0x0000,gr8
+
+	set_gr_limmed	0x0000,0xffff,gr8
+	set_icc         0x0d,1		; Set mask opposite of expected
+	candcc		gr7,gr8,gr8,cc5,1
+	test_icc	1 1 0 1 icc1
+	test_gr_limmed	0x0000,0xffff,gr8
+
+	set_gr_limmed  	0xaaaa,0xaaaa,gr7
+	set_gr_limmed  	0x5555,0x5555,gr8
+	set_icc         0x0b,2		; Set mask opposite of expected
+	candcc      	gr7,gr8,gr8,cc2,0
+	test_icc	1 0 1 1 icc2
+	test_gr_limmed 	0x5555,0x5555,gr8
+
+	set_gr_limmed  	0xffff,0x0000,gr8
+	set_icc         0x04,2		; Set mask opposite of expected
+	candcc		gr7,gr8,gr8,cc2,0
+	test_icc	0 1 0 0 icc2
+	test_gr_limmed 	0xffff,0x0000,gr8
+
+	set_gr_limmed	0x0000,0xffff,gr8
+	set_icc         0x0d,2		; Set mask opposite of expected
+	candcc		gr7,gr8,gr8,cc6,1
+	test_icc	1 1 0 1 icc2
+	test_gr_limmed	0x0000,0xffff,gr8
+
+	set_gr_limmed  	0xaaaa,0xaaaa,gr7
+	set_gr_limmed  	0x5555,0x5555,gr8
+	set_icc         0x0b,3		; Set mask opposite of expected
+	candcc      	gr7,gr8,gr8,cc3,0
+	test_icc	1 0 1 1 icc3
+	test_gr_limmed 	0x5555,0x5555,gr8
+
+	set_gr_limmed  	0xffff,0x0000,gr8
+	set_icc         0x04,3		; Set mask opposite of expected
+	candcc		gr7,gr8,gr8,cc3,0
+	test_icc	0 1 0 0 icc3
+	test_gr_limmed 	0xffff,0x0000,gr8
+
+	set_gr_limmed	0x0000,0xffff,gr8
+	set_icc         0x0d,3		; Set mask opposite of expected
+	candcc		gr7,gr8,gr8,cc7,1
+	test_icc	1 1 0 1 icc3
+	test_gr_limmed	0x0000,0xffff,gr8
+
+	pass