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-rw-r--r--sim/or1k/sem-switch.c281
1 files changed, 228 insertions, 53 deletions
diff --git a/sim/or1k/sem-switch.c b/sim/or1k/sem-switch.c
index 2f8e0f3..2045567 100644
--- a/sim/or1k/sem-switch.c
+++ b/sim/or1k/sem-switch.c
@@ -39,6 +39,7 @@ This file is part of the GNU simulators.
{ OR1K32BF_INSN_X_CHAIN, && case_sem_INSN_X_CHAIN },
{ OR1K32BF_INSN_X_BEGIN, && case_sem_INSN_X_BEGIN },
{ OR1K32BF_INSN_L_J, && case_sem_INSN_L_J },
+ { OR1K32BF_INSN_L_ADRP, && case_sem_INSN_L_ADRP },
{ OR1K32BF_INSN_L_JAL, && case_sem_INSN_L_JAL },
{ OR1K32BF_INSN_L_JR, && case_sem_INSN_L_JR },
{ OR1K32BF_INSN_L_JALR, && case_sem_INSN_L_JALR },
@@ -81,7 +82,9 @@ This file is part of the GNU simulators.
{ OR1K32BF_INSN_L_SUB, && case_sem_INSN_L_SUB },
{ OR1K32BF_INSN_L_ADDC, && case_sem_INSN_L_ADDC },
{ OR1K32BF_INSN_L_MUL, && case_sem_INSN_L_MUL },
+ { OR1K32BF_INSN_L_MULD, && case_sem_INSN_L_MULD },
{ OR1K32BF_INSN_L_MULU, && case_sem_INSN_L_MULU },
+ { OR1K32BF_INSN_L_MULDU, && case_sem_INSN_L_MULDU },
{ OR1K32BF_INSN_L_DIV, && case_sem_INSN_L_DIV },
{ OR1K32BF_INSN_L_DIVU, && case_sem_INSN_L_DIVU },
{ OR1K32BF_INSN_L_FF1, && case_sem_INSN_L_FF1 },
@@ -120,8 +123,10 @@ This file is part of the GNU simulators.
{ OR1K32BF_INSN_L_SFNE, && case_sem_INSN_L_SFNE },
{ OR1K32BF_INSN_L_SFNEI, && case_sem_INSN_L_SFNEI },
{ OR1K32BF_INSN_L_MAC, && case_sem_INSN_L_MAC },
- { OR1K32BF_INSN_L_MSB, && case_sem_INSN_L_MSB },
{ OR1K32BF_INSN_L_MACI, && case_sem_INSN_L_MACI },
+ { OR1K32BF_INSN_L_MACU, && case_sem_INSN_L_MACU },
+ { OR1K32BF_INSN_L_MSB, && case_sem_INSN_L_MSB },
+ { OR1K32BF_INSN_L_MSBU, && case_sem_INSN_L_MSBU },
{ OR1K32BF_INSN_L_CUST1, && case_sem_INSN_L_CUST1 },
{ OR1K32BF_INSN_L_CUST2, && case_sem_INSN_L_CUST2 },
{ OR1K32BF_INSN_L_CUST3, && case_sem_INSN_L_CUST3 },
@@ -373,6 +378,25 @@ if (1)
}
NEXT (vpc);
+ CASE (sem, INSN_L_ADRP) : /* l.adrp $rD,${disp21} */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_l_adrp.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+ {
+ USI opval = FLD (i_disp21);
+ SET_H_GPR (FLD (f_r1), opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "gpr", 'x', opval);
+ }
+
+#undef FLD
+}
+ NEXT (vpc);
+
CASE (sem, INSN_L_JAL) : /* l.jal ${disp26} */
{
SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
@@ -690,7 +714,7 @@ or1k32bf_nop (current_cpu, ZEXTSISI (FLD (f_uimm16)));
{
SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.sfmt_l_slli.f
+#define FLD(f) abuf->fields.sfmt_l_adrp.f
int UNUSED written = 0;
IADDR UNUSED pc = abuf->addr;
vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
@@ -1366,11 +1390,6 @@ or1k32bf_exception (current_cpu, pc, EXCEPT_RANGE);
CGEN_TRACE_RESULT (current_cpu, abuf, "sys-sr-ov", 'x', opval);
}
{
- BI opval = MUL1OFSI (GET_H_GPR (FLD (f_r2)), GET_H_GPR (FLD (f_r3)));
- SET_H_SYS_SR_CY (opval);
- CGEN_TRACE_RESULT (current_cpu, abuf, "sys-sr-cy", 'x', opval);
- }
- {
USI opval = MULSI (GET_H_GPR (FLD (f_r2)), GET_H_GPR (FLD (f_r3)));
SET_H_GPR (FLD (f_r1), opval);
CGEN_TRACE_RESULT (current_cpu, abuf, "gpr", 'x', opval);
@@ -1385,7 +1404,7 @@ or1k32bf_exception (current_cpu, pc, EXCEPT_RANGE);
}
NEXT (vpc);
- CASE (sem, INSN_L_MULU) : /* l.mulu $rD,$rA,$rB */
+ CASE (sem, INSN_L_MULD) : /* l.muld $rA,$rB */
{
SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
ARGBUF *abuf = SEM_ARGBUF (sem_arg);
@@ -1395,12 +1414,35 @@ or1k32bf_exception (current_cpu, pc, EXCEPT_RANGE);
vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
{
-{
+ DI tmp_result;
+ tmp_result = MULDI (EXTSIDI (GET_H_GPR (FLD (f_r2))), EXTSIDI (GET_H_GPR (FLD (f_r3))));
{
- BI opval = 0;
- SET_H_SYS_SR_OV (opval);
- CGEN_TRACE_RESULT (current_cpu, abuf, "sys-sr-ov", 'x', opval);
+ SI opval = SUBWORDDISI (tmp_result, 0);
+ SET_H_MAC_MACHI (opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "mac-machi", 'x', opval);
+ }
+ {
+ SI opval = SUBWORDDISI (tmp_result, 1);
+ SET_H_MAC_MACLO (opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "mac-maclo", 'x', opval);
}
+}
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_L_MULU) : /* l.mulu $rD,$rA,$rB */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_l_sll.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+{
{
BI opval = MUL1OFSI (GET_H_GPR (FLD (f_r2)), GET_H_GPR (FLD (f_r3)));
SET_H_SYS_SR_CY (opval);
@@ -1412,7 +1454,7 @@ or1k32bf_exception (current_cpu, pc, EXCEPT_RANGE);
CGEN_TRACE_RESULT (current_cpu, abuf, "gpr", 'x', opval);
}
}
-if (ANDIF (GET_H_SYS_SR_OV (), GET_H_SYS_SR_OVE ())) {
+if (ANDIF (GET_H_SYS_SR_CY (), GET_H_SYS_SR_OVE ())) {
or1k32bf_exception (current_cpu, pc, EXCEPT_RANGE);
}
}
@@ -1421,7 +1463,7 @@ or1k32bf_exception (current_cpu, pc, EXCEPT_RANGE);
}
NEXT (vpc);
- CASE (sem, INSN_L_DIV) : /* l.div $rD,$rA,$rB */
+ CASE (sem, INSN_L_MULDU) : /* l.muldu $rA,$rB */
{
SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
ARGBUF *abuf = SEM_ARGBUF (sem_arg);
@@ -1431,38 +1473,61 @@ or1k32bf_exception (current_cpu, pc, EXCEPT_RANGE);
vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
{
+ DI tmp_result;
+ tmp_result = MULDI (ZEXTSIDI (GET_H_GPR (FLD (f_r2))), ZEXTSIDI (GET_H_GPR (FLD (f_r3))));
+ {
+ SI opval = SUBWORDDISI (tmp_result, 0);
+ SET_H_MAC_MACHI (opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "mac-machi", 'x', opval);
+ }
+ {
+ SI opval = SUBWORDDISI (tmp_result, 1);
+ SET_H_MAC_MACLO (opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "mac-maclo", 'x', opval);
+ }
+}
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_L_DIV) : /* l.div $rD,$rA,$rB */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_l_sll.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
if (NESI (GET_H_GPR (FLD (f_r3)), 0)) {
{
{
BI opval = 0;
- SET_H_SYS_SR_CY (opval);
- written |= (1 << 6);
- CGEN_TRACE_RESULT (current_cpu, abuf, "sys-sr-cy", 'x', opval);
+ SET_H_SYS_SR_OV (opval);
+ written |= (1 << 5);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "sys-sr-ov", 'x', opval);
}
{
SI opval = DIVSI (GET_H_GPR (FLD (f_r2)), GET_H_GPR (FLD (f_r3)));
SET_H_GPR (FLD (f_r1), opval);
- written |= (1 << 5);
+ written |= (1 << 4);
CGEN_TRACE_RESULT (current_cpu, abuf, "gpr", 'x', opval);
}
}
} else {
+{
{
BI opval = 1;
- SET_H_SYS_SR_CY (opval);
- written |= (1 << 6);
- CGEN_TRACE_RESULT (current_cpu, abuf, "sys-sr-cy", 'x', opval);
- }
-}
- {
- BI opval = 0;
SET_H_SYS_SR_OV (opval);
+ written |= (1 << 5);
CGEN_TRACE_RESULT (current_cpu, abuf, "sys-sr-ov", 'x', opval);
}
-if (ANDIF (GET_H_SYS_SR_CY (), GET_H_SYS_SR_OVE ())) {
+if (GET_H_SYS_SR_OVE ()) {
or1k32bf_exception (current_cpu, pc, EXCEPT_RANGE);
}
}
+}
abuf->written = written;
#undef FLD
@@ -1478,39 +1543,34 @@ or1k32bf_exception (current_cpu, pc, EXCEPT_RANGE);
IADDR UNUSED pc = abuf->addr;
vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
-{
if (NESI (GET_H_GPR (FLD (f_r3)), 0)) {
{
{
BI opval = 0;
SET_H_SYS_SR_CY (opval);
- written |= (1 << 6);
+ written |= (1 << 5);
CGEN_TRACE_RESULT (current_cpu, abuf, "sys-sr-cy", 'x', opval);
}
{
USI opval = UDIVSI (GET_H_GPR (FLD (f_r2)), GET_H_GPR (FLD (f_r3)));
SET_H_GPR (FLD (f_r1), opval);
- written |= (1 << 5);
+ written |= (1 << 4);
CGEN_TRACE_RESULT (current_cpu, abuf, "gpr", 'x', opval);
}
}
} else {
+{
{
BI opval = 1;
SET_H_SYS_SR_CY (opval);
- written |= (1 << 6);
+ written |= (1 << 5);
CGEN_TRACE_RESULT (current_cpu, abuf, "sys-sr-cy", 'x', opval);
}
-}
- {
- BI opval = 0;
- SET_H_SYS_SR_OV (opval);
- CGEN_TRACE_RESULT (current_cpu, abuf, "sys-sr-ov", 'x', opval);
- }
-if (ANDIF (GET_H_SYS_SR_CY (), GET_H_SYS_SR_OVE ())) {
+if (GET_H_SYS_SR_OVE ()) {
or1k32bf_exception (current_cpu, pc, EXCEPT_RANGE);
}
}
+}
abuf->written = written;
#undef FLD
@@ -1703,11 +1763,6 @@ or1k32bf_exception (current_cpu, pc, EXCEPT_RANGE);
CGEN_TRACE_RESULT (current_cpu, abuf, "sys-sr-ov", 'x', opval);
}
{
- USI opval = MUL1OFSI (GET_H_GPR (FLD (f_r2)), EXTSISI (FLD (f_simm16)));
- SET_H_SYS_SR_CY (opval);
- CGEN_TRACE_RESULT (current_cpu, abuf, "sys-sr-cy", 'x', opval);
- }
- {
USI opval = MULSI (GET_H_GPR (FLD (f_r2)), EXTSISI (FLD (f_simm16)));
SET_H_GPR (FLD (f_r1), opval);
CGEN_TRACE_RESULT (current_cpu, abuf, "gpr", 'x', opval);
@@ -2256,10 +2311,97 @@ if (GET_H_SYS_SR_F ()) {
vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
{
- SI tmp_prod;
+{
+ DI tmp_prod;
+ DI tmp_mac;
+ DI tmp_result;
+ tmp_prod = MULDI (EXTSIDI (GET_H_GPR (FLD (f_r2))), EXTSIDI (GET_H_GPR (FLD (f_r3))));
+ tmp_mac = JOINSIDI (GET_H_MAC_MACHI (), GET_H_MAC_MACLO ());
+ tmp_result = ADDDI (tmp_prod, tmp_mac);
+ {
+ SI opval = SUBWORDDISI (tmp_result, 0);
+ SET_H_MAC_MACHI (opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "mac-machi", 'x', opval);
+ }
+ {
+ SI opval = SUBWORDDISI (tmp_result, 1);
+ SET_H_MAC_MACLO (opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "mac-maclo", 'x', opval);
+ }
+ {
+ BI opval = ADDOFDI (tmp_prod, tmp_mac, 0);
+ SET_H_SYS_SR_OV (opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "sys-sr-ov", 'x', opval);
+ }
+}
+if (ANDIF (GET_H_SYS_SR_OV (), GET_H_SYS_SR_OVE ())) {
+or1k32bf_exception (current_cpu, pc, EXCEPT_RANGE);
+}
+}
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_L_MACI) : /* l.maci $rA,${simm16} */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_l_lwz.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+{
+ DI tmp_prod;
+ DI tmp_mac;
+ DI tmp_result;
+ tmp_prod = MULDI (EXTSIDI (GET_H_GPR (FLD (f_r2))), EXTSIDI (FLD (f_simm16)));
+ tmp_mac = JOINSIDI (GET_H_MAC_MACHI (), GET_H_MAC_MACLO ());
+ tmp_result = ADDDI (tmp_mac, tmp_prod);
+ {
+ SI opval = SUBWORDDISI (tmp_result, 0);
+ SET_H_MAC_MACHI (opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "mac-machi", 'x', opval);
+ }
+ {
+ SI opval = SUBWORDDISI (tmp_result, 1);
+ SET_H_MAC_MACLO (opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "mac-maclo", 'x', opval);
+ }
+ {
+ BI opval = ADDOFDI (tmp_prod, tmp_mac, 0);
+ SET_H_SYS_SR_OV (opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "sys-sr-ov", 'x', opval);
+ }
+}
+if (ANDIF (GET_H_SYS_SR_OV (), GET_H_SYS_SR_OVE ())) {
+or1k32bf_exception (current_cpu, pc, EXCEPT_RANGE);
+}
+}
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_L_MACU) : /* l.macu $rA,$rB */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_l_sll.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+{
+ DI tmp_prod;
+ DI tmp_mac;
DI tmp_result;
- tmp_prod = MULSI (GET_H_GPR (FLD (f_r2)), GET_H_GPR (FLD (f_r3)));
- tmp_result = ADDDI (JOINSIDI (GET_H_MAC_MACHI (), GET_H_MAC_MACLO ()), EXTSIDI (tmp_prod));
+ tmp_prod = MULDI (ZEXTSIDI (GET_H_GPR (FLD (f_r2))), ZEXTSIDI (GET_H_GPR (FLD (f_r3))));
+ tmp_mac = JOINSIDI (GET_H_MAC_MACHI (), GET_H_MAC_MACLO ());
+ tmp_result = ADDDI (tmp_prod, tmp_mac);
{
SI opval = SUBWORDDISI (tmp_result, 0);
SET_H_MAC_MACHI (opval);
@@ -2270,6 +2412,15 @@ if (GET_H_SYS_SR_F ()) {
SET_H_MAC_MACLO (opval);
CGEN_TRACE_RESULT (current_cpu, abuf, "mac-maclo", 'x', opval);
}
+ {
+ BI opval = ADDCFDI (tmp_prod, tmp_mac, 0);
+ SET_H_SYS_SR_CY (opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "sys-sr-cy", 'x', opval);
+ }
+}
+if (ANDIF (GET_H_SYS_SR_CY (), GET_H_SYS_SR_OVE ())) {
+or1k32bf_exception (current_cpu, pc, EXCEPT_RANGE);
+}
}
#undef FLD
@@ -2286,10 +2437,13 @@ if (GET_H_SYS_SR_F ()) {
vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
{
- SI tmp_prod;
+{
+ DI tmp_prod;
+ DI tmp_mac;
DI tmp_result;
- tmp_prod = MULSI (GET_H_GPR (FLD (f_r2)), GET_H_GPR (FLD (f_r3)));
- tmp_result = SUBDI (JOINSIDI (GET_H_MAC_MACHI (), GET_H_MAC_MACLO ()), EXTSIDI (tmp_prod));
+ tmp_prod = MULDI (EXTSIDI (GET_H_GPR (FLD (f_r2))), EXTSIDI (GET_H_GPR (FLD (f_r3))));
+ tmp_mac = JOINSIDI (GET_H_MAC_MACHI (), GET_H_MAC_MACLO ());
+ tmp_result = SUBDI (tmp_mac, tmp_prod);
{
SI opval = SUBWORDDISI (tmp_result, 0);
SET_H_MAC_MACHI (opval);
@@ -2300,26 +2454,38 @@ if (GET_H_SYS_SR_F ()) {
SET_H_MAC_MACLO (opval);
CGEN_TRACE_RESULT (current_cpu, abuf, "mac-maclo", 'x', opval);
}
+ {
+ BI opval = SUBOFDI (tmp_mac, tmp_result, 0);
+ SET_H_SYS_SR_OV (opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "sys-sr-ov", 'x', opval);
+ }
+}
+if (ANDIF (GET_H_SYS_SR_OV (), GET_H_SYS_SR_OVE ())) {
+or1k32bf_exception (current_cpu, pc, EXCEPT_RANGE);
+}
}
#undef FLD
}
NEXT (vpc);
- CASE (sem, INSN_L_MACI) : /* l.maci $rA,${simm16} */
+ CASE (sem, INSN_L_MSBU) : /* l.msbu $rA,$rB */
{
SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.sfmt_l_lwz.f
+#define FLD(f) abuf->fields.sfmt_l_sll.f
int UNUSED written = 0;
IADDR UNUSED pc = abuf->addr;
vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
{
- SI tmp_prod;
+{
+ DI tmp_prod;
+ DI tmp_mac;
DI tmp_result;
- tmp_prod = MULSI (EXTSISI (FLD (f_simm16)), GET_H_GPR (FLD (f_r2)));
- tmp_result = ADDDI (JOINSIDI (GET_H_MAC_MACHI (), GET_H_MAC_MACLO ()), EXTSIDI (tmp_prod));
+ tmp_prod = MULDI (ZEXTSIDI (GET_H_GPR (FLD (f_r2))), ZEXTSIDI (GET_H_GPR (FLD (f_r3))));
+ tmp_mac = JOINSIDI (GET_H_MAC_MACHI (), GET_H_MAC_MACLO ());
+ tmp_result = SUBDI (tmp_mac, tmp_prod);
{
SI opval = SUBWORDDISI (tmp_result, 0);
SET_H_MAC_MACHI (opval);
@@ -2330,6 +2496,15 @@ if (GET_H_SYS_SR_F ()) {
SET_H_MAC_MACLO (opval);
CGEN_TRACE_RESULT (current_cpu, abuf, "mac-maclo", 'x', opval);
}
+ {
+ BI opval = SUBCFDI (tmp_mac, tmp_result, 0);
+ SET_H_SYS_SR_CY (opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "sys-sr-cy", 'x', opval);
+ }
+}
+if (ANDIF (GET_H_SYS_SR_CY (), GET_H_SYS_SR_OVE ())) {
+or1k32bf_exception (current_cpu, pc, EXCEPT_RANGE);
+}
}
#undef FLD
generated by cgit v1.1 at 2025-02-23 17:15:23 +0000