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Diffstat (limited to 'sim/erc32/erc32.c')
-rw-r--r--sim/erc32/erc32.c234
1 files changed, 117 insertions, 117 deletions
diff --git a/sim/erc32/erc32.c b/sim/erc32/erc32.c
index 8789cbc..0206c02 100644
--- a/sim/erc32/erc32.c
+++ b/sim/erc32/erc32.c
@@ -34,8 +34,8 @@
#include "sim-config.h"
extern int ctrl_c;
-extern int32 sis_verbose;
-extern int32 sparclite, sparclite_board;
+extern int32_t sis_verbose;
+extern int32_t sparclite, sparclite_board;
extern int rom8,wrp,uben;
extern char uart_dev1[], uart_dev2[];
@@ -147,45 +147,45 @@ extern int errmec;
/* MEC registers */
static char fname[256];
-static int32 find = 0;
-static uint32 mec_ssa[2]; /* Write protection start address */
-static uint32 mec_sea[2]; /* Write protection end address */
-static uint32 mec_wpr[2]; /* Write protection control fields */
-static uint32 mec_sfsr;
-static uint32 mec_ffar;
-static uint32 mec_ipr;
-static uint32 mec_imr;
-static uint32 mec_isr;
-static uint32 mec_icr;
-static uint32 mec_ifr;
-static uint32 mec_mcr; /* MEC control register */
-static uint32 mec_memcfg; /* Memory control register */
-static uint32 mec_wcr; /* MEC waitstate register */
-static uint32 mec_iocr; /* MEC IO control register */
-static uint32 posted_irq;
-static uint32 mec_ersr; /* MEC error and status register */
-static uint32 mec_tcr; /* MEC test comtrol register */
-
-static uint32 rtc_counter;
-static uint32 rtc_reload;
-static uint32 rtc_scaler;
-static uint32 rtc_scaler_start;
-static uint32 rtc_enabled;
-static uint32 rtc_cr;
-static uint32 rtc_se;
-
-static uint32 gpt_counter;
-static uint32 gpt_reload;
-static uint32 gpt_scaler;
-static uint32 gpt_scaler_start;
-static uint32 gpt_enabled;
-static uint32 gpt_cr;
-static uint32 gpt_se;
-
-static uint32 wdog_scaler;
-static uint32 wdog_counter;
-static uint32 wdog_rst_delay;
-static uint32 wdog_rston;
+static int32_t find = 0;
+static uint32_t mec_ssa[2]; /* Write protection start address */
+static uint32_t mec_sea[2]; /* Write protection end address */
+static uint32_t mec_wpr[2]; /* Write protection control fields */
+static uint32_t mec_sfsr;
+static uint32_t mec_ffar;
+static uint32_t mec_ipr;
+static uint32_t mec_imr;
+static uint32_t mec_isr;
+static uint32_t mec_icr;
+static uint32_t mec_ifr;
+static uint32_t mec_mcr; /* MEC control register */
+static uint32_t mec_memcfg; /* Memory control register */
+static uint32_t mec_wcr; /* MEC waitstate register */
+static uint32_t mec_iocr; /* MEC IO control register */
+static uint32_t posted_irq;
+static uint32_t mec_ersr; /* MEC error and status register */
+static uint32_t mec_tcr; /* MEC test comtrol register */
+
+static uint32_t rtc_counter;
+static uint32_t rtc_reload;
+static uint32_t rtc_scaler;
+static uint32_t rtc_scaler_start;
+static uint32_t rtc_enabled;
+static uint32_t rtc_cr;
+static uint32_t rtc_se;
+
+static uint32_t gpt_counter;
+static uint32_t gpt_reload;
+static uint32_t gpt_scaler;
+static uint32_t gpt_scaler_start;
+static uint32_t gpt_enabled;
+static uint32_t gpt_cr;
+static uint32_t gpt_se;
+
+static uint32_t wdog_scaler;
+static uint32_t wdog_counter;
+static uint32_t wdog_rst_delay;
+static uint32_t wdog_rston;
enum wdog_type {
init, disabled, enabled, stopped
@@ -210,17 +210,17 @@ static enum wdog_type wdog_status;
/* Memory support variables */
-static uint32 mem_ramr_ws; /* RAM read waitstates */
-static uint32 mem_ramw_ws; /* RAM write waitstates */
-static uint32 mem_romr_ws; /* ROM read waitstates */
-static uint32 mem_romw_ws; /* ROM write waitstates */
-static uint32 mem_ramstart; /* RAM start */
-static uint32 mem_ramend; /* RAM end */
-static uint32 mem_rammask; /* RAM address mask */
-static uint32 mem_ramsz; /* RAM size */
-static uint32 mem_romsz; /* ROM size */
-static uint32 mem_accprot; /* RAM write protection enabled */
-static uint32 mem_blockprot; /* RAM block write protection enabled */
+static uint32_t mem_ramr_ws; /* RAM read waitstates */
+static uint32_t mem_ramw_ws; /* RAM write waitstates */
+static uint32_t mem_romr_ws; /* ROM read waitstates */
+static uint32_t mem_romw_ws; /* ROM write waitstates */
+static uint32_t mem_ramstart; /* RAM start */
+static uint32_t mem_ramend; /* RAM end */
+static uint32_t mem_rammask; /* RAM address mask */
+static uint32_t mem_ramsz; /* RAM size */
+static uint32_t mem_romsz; /* ROM size */
+static uint32_t mem_accprot; /* RAM write protection enabled */
+static uint32_t mem_blockprot; /* RAM block write protection enabled */
static unsigned char romb[ROM_SZ];
static unsigned char ramb[RAM_END - RAM_START];
@@ -228,11 +228,11 @@ static unsigned char ramb[RAM_END - RAM_START];
/* UART support variables */
-static int32 fd1, fd2; /* file descriptor for input file */
-static int32 Ucontrol; /* UART status register */
+static int32_t fd1, fd2; /* file descriptor for input file */
+static int32_t Ucontrol; /* UART status register */
static unsigned char aq[UARTBUF], bq[UARTBUF];
-static int32 anum, aind = 0;
-static int32 bnum, bind = 0;
+static int32_t anum, aind = 0;
+static int32_t bnum, bind = 0;
static char wbufa[UARTBUF], wbufb[UARTBUF];
static unsigned wnuma;
static unsigned wnumb;
@@ -243,8 +243,8 @@ static struct termios ioc1, ioc2, iocold1, iocold2;
static int f1open = 0, f2open = 0;
static char uarta_sreg, uarta_hreg, uartb_sreg, uartb_hreg;
-static uint32 uart_stat_reg;
-static uint32 uarta_data, uartb_data;
+static uint32_t uart_stat_reg;
+static uint32_t uarta_data, uartb_data;
#ifdef ERA
int era = 0;
@@ -263,16 +263,16 @@ static void decode_wcr (void);
static void decode_mcr (void);
static void close_port (void);
static void mec_reset (void);
-static void mec_intack (int32 level);
+static void mec_intack (int32_t level);
static void chk_irq (void);
-static void mec_irq (int32 level);
-static void set_sfsr (uint32 fault, uint32 addr,
- uint32 asi, uint32 read);
-static int32 mec_read (uint32 addr, uint32 asi, uint32 *data);
-static int mec_write (uint32 addr, uint32 data);
+static void mec_irq (int32_t level);
+static void set_sfsr (uint32_t fault, uint32_t addr,
+ uint32_t asi, uint32_t read);
+static int32_t mec_read (uint32_t addr, uint32_t asi, uint32_t *data);
+static int mec_write (uint32_t addr, uint32_t data);
static void port_init (void);
-static uint32 read_uart (uint32 addr);
-static void write_uart (uint32 addr, uint32 data);
+static uint32_t read_uart (uint32_t addr);
+static void write_uart (uint32_t addr, uint32_t data);
static void flush_uart (void);
static void uarta_tx (void);
static void uartb_tx (void);
@@ -283,18 +283,18 @@ static void wdog_intr (void *arg);
static void wdog_start (void);
static void rtc_intr (void *arg);
static void rtc_start (void);
-static uint32 rtc_counter_read (void);
-static void rtc_scaler_set (uint32 val);
-static void rtc_reload_set (uint32 val);
+static uint32_t rtc_counter_read (void);
+static void rtc_scaler_set (uint32_t val);
+static void rtc_reload_set (uint32_t val);
static void gpt_intr (void *arg);
static void gpt_start (void);
-static uint32 gpt_counter_read (void);
-static void gpt_scaler_set (uint32 val);
-static void gpt_reload_set (uint32 val);
-static void timer_ctrl (uint32 val);
-static void * get_mem_ptr (uint32 addr, uint32 size);
-static void store_bytes (unsigned char *mem, uint32 waddr,
- uint32 *data, int sz, int32 *ws);
+static uint32_t gpt_counter_read (void);
+static void gpt_scaler_set (uint32_t val);
+static void gpt_reload_set (uint32_t val);
+static void timer_ctrl (uint32_t val);
+static void * get_mem_ptr (uint32_t addr, uint32_t size);
+static void store_bytes (unsigned char *mem, uint32_t waddr,
+ uint32_t *data, int sz, int32_t *ws);
extern int ext_irl;
@@ -390,7 +390,7 @@ mecparerror(void)
/* IU error mode manager */
void
-error_mode(uint32 pc)
+error_mode(uint32_t pc)
{
mec_ersr |= 0x1;
@@ -551,7 +551,7 @@ mec_reset(void)
static void
-mec_intack(int32 level)
+mec_intack(int32_t level)
{
int irq_test;
@@ -568,8 +568,8 @@ mec_intack(int32 level)
static void
chk_irq(void)
{
- int32 i;
- uint32 itmp;
+ int32_t i;
+ uint32_t itmp;
int old_irl;
old_irl = ext_irl;
@@ -591,14 +591,14 @@ chk_irq(void)
}
static void
-mec_irq(int32 level)
+mec_irq(int32_t level)
{
mec_ipr |= (1 << level);
chk_irq();
}
static void
-set_sfsr(uint32 fault, uint32 addr, uint32 asi, uint32 read)
+set_sfsr(uint32_t fault, uint32_t addr, uint32_t asi, uint32_t read)
{
if ((asi == 0xa) || (asi == 0xb)) {
mec_ffar = addr;
@@ -615,8 +615,8 @@ set_sfsr(uint32 fault, uint32 addr, uint32 asi, uint32 read)
}
}
-static int32
-mec_read(uint32 addr, uint32 asi, uint32 *data)
+static int32_t
+mec_read(uint32_t addr, uint32_t asi, uint32_t *data)
{
switch (addr & 0x0ff) {
@@ -743,7 +743,7 @@ mec_read(uint32 addr, uint32 asi, uint32 *data)
}
static int
-mec_write(uint32 addr, uint32 data)
+mec_write(uint32_t addr, uint32_t data)
{
if (sis_verbose > 1)
printf("MEC write a: %08x, d: %08x\n",addr,data);
@@ -1039,8 +1039,8 @@ port_init(void)
}
-static uint32
-read_uart(uint32 addr)
+static uint32_t
+read_uart(uint32_t addr)
{
unsigned tmp;
@@ -1055,7 +1055,7 @@ read_uart(uint32 addr)
if (aind < anum) {
if ((aind + 1) < anum)
mec_irq(4);
- return (0x700 | (uint32) aq[aind++]);
+ return (0x700 | (uint32_t) aq[aind++]);
} else {
if (f1open) {
anum = DO_STDIO_READ(ifd1, aq, UARTBUF);
@@ -1064,9 +1064,9 @@ read_uart(uint32 addr)
aind = 0;
if ((aind + 1) < anum)
mec_irq(4);
- return (0x700 | (uint32) aq[aind++]);
+ return (0x700 | (uint32_t) aq[aind++]);
} else {
- return (0x600 | (uint32) aq[aind]);
+ return (0x600 | (uint32_t) aq[aind]);
}
}
@@ -1087,7 +1087,7 @@ read_uart(uint32 addr)
if (bind < bnum) {
if ((bind + 1) < bnum)
mec_irq(5);
- return (0x700 | (uint32) bq[bind++]);
+ return (0x700 | (uint32_t) bq[bind++]);
} else {
if (f2open) {
bnum = DO_STDIO_READ(ifd2, bq, UARTBUF);
@@ -1096,9 +1096,9 @@ read_uart(uint32 addr)
bind = 0;
if ((bind + 1) < bnum)
mec_irq(5);
- return (0x700 | (uint32) bq[bind++]);
+ return (0x700 | (uint32_t) bq[bind++]);
} else {
- return (0x600 | (uint32) bq[bind]);
+ return (0x600 | (uint32_t) bq[bind]);
}
}
@@ -1161,7 +1161,7 @@ read_uart(uint32 addr)
}
static void
-write_uart(uint32 addr, uint32 data)
+write_uart(uint32_t addr, uint32_t data)
{
unsigned char c;
@@ -1278,7 +1278,7 @@ ATTRIBUTE_UNUSED
static void
uart_rx(void *arg)
{
- int32 rsize;
+ int32_t rsize;
char rxd;
@@ -1411,20 +1411,20 @@ rtc_start(void)
rtc_enabled = 1;
}
-static uint32
+static uint32_t
rtc_counter_read(void)
{
return rtc_counter;
}
static void
-rtc_scaler_set(uint32 val)
+rtc_scaler_set(uint32_t val)
{
rtc_scaler = val & 0x0ff; /* eight-bit scaler only */
}
static void
-rtc_reload_set(uint32 val)
+rtc_reload_set(uint32_t val)
{
rtc_reload = val;
}
@@ -1461,26 +1461,26 @@ gpt_start(void)
gpt_enabled = 1;
}
-static uint32
+static uint32_t
gpt_counter_read(void)
{
return gpt_counter;
}
static void
-gpt_scaler_set(uint32 val)
+gpt_scaler_set(uint32_t val)
{
gpt_scaler = val & 0x0ffff; /* 16-bit scaler */
}
static void
-gpt_reload_set(uint32 val)
+gpt_reload_set(uint32_t val)
{
gpt_reload = val;
}
static void
-timer_ctrl(uint32 val)
+timer_ctrl(uint32_t val)
{
rtc_cr = ((val & TCR_TCRCR) != 0);
@@ -1512,8 +1512,8 @@ timer_ctrl(uint32 val)
wait-states. */
static void
-store_bytes (unsigned char *mem, uint32 waddr, uint32 *data, int32 sz,
- int32 *ws)
+store_bytes (unsigned char *mem, uint32_t waddr, uint32_t *data, int32_t sz,
+ int32_t *ws)
{
switch (sz) {
case 0:
@@ -1543,9 +1543,9 @@ store_bytes (unsigned char *mem, uint32 waddr, uint32 *data, int32 sz,
/* Memory emulation */
int
-memory_iread (uint32 addr, uint32 *data, uint32 *ws)
+memory_iread (uint32_t addr, uint32_t *data, uint32_t *ws)
{
- uint32 asi;
+ uint32_t asi;
if ((addr >= mem_ramstart) && (addr < (mem_ramstart + mem_ramsz))) {
memcpy (data, &ramb[addr & mem_rammask & ~3], 4);
*ws = mem_ramr_ws;
@@ -1568,9 +1568,9 @@ memory_iread (uint32 addr, uint32 *data, uint32 *ws)
}
int
-memory_read(int32 asi, uint32 addr, void *data, int32 sz, int32 *ws)
+memory_read(int32_t asi, uint32_t addr, void *data, int32_t sz, int32_t *ws)
{
- int32 mexc;
+ int32_t mexc;
#ifdef ERRINJ
if (errmec) {
@@ -1634,13 +1634,13 @@ memory_read(int32 asi, uint32 addr, void *data, int32 sz, int32 *ws)
}
int
-memory_write(int32 asi, uint32 addr, uint32 *data, int32 sz, int32 *ws)
+memory_write(int32_t asi, uint32_t addr, uint32_t *data, int32_t sz, int32_t *ws)
{
- uint32 byte_addr;
- uint32 byte_mask;
- uint32 waddr;
- uint32 *ram;
- int32 mexc;
+ uint32_t byte_addr;
+ uint32_t byte_mask;
+ uint32_t waddr;
+ uint32_t *ram;
+ int32_t mexc;
int i;
int wphit[2];
@@ -1742,7 +1742,7 @@ memory_write(int32 asi, uint32 addr, uint32 *data, int32 sz, int32 *ws)
}
static void *
-get_mem_ptr(uint32 addr, uint32 size)
+get_mem_ptr(uint32_t addr, uint32_t size)
{
if ((addr + size) < ROM_SZ) {
return &romb[addr];
@@ -1761,7 +1761,7 @@ get_mem_ptr(uint32 addr, uint32 size)
}
int
-sis_memory_write(uint32 addr, const void *data, uint32 length)
+sis_memory_write(uint32_t addr, const void *data, uint32_t length)
{
void *mem;
@@ -1773,7 +1773,7 @@ sis_memory_write(uint32 addr, const void *data, uint32 length)
}
int
-sis_memory_read(uint32 addr, void *data, uint32 length)
+sis_memory_read(uint32_t addr, void *data, uint32_t length)
{
char *mem;
generated by cgit v1.1 at 2024-08-16 21:38:59 +0000