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-rw-r--r--opcodes/riscv-dis.c27
1 files changed, 27 insertions, 0 deletions
diff --git a/opcodes/riscv-dis.c b/opcodes/riscv-dis.c
index f7f4c07..cb521dc 100644
--- a/opcodes/riscv-dis.c
+++ b/opcodes/riscv-dis.c
@@ -702,6 +702,33 @@ print_insn_args (const char *oparg, insn_t l, bfd_vma pc, disassemble_info *info
goto undefined_modifier;
}
break;
+ case 's': /* Vendor-specific (SiFive) operands. */
+ switch (*++oparg)
+ {
+ /* SiFive vector coprocessor interface. */
+ case 'd':
+ print (info->stream, dis_style_register, "0x%x",
+ (unsigned) EXTRACT_OPERAND (RD, l));
+ break;
+ case 't':
+ print (info->stream, dis_style_register, "0x%x",
+ (unsigned) EXTRACT_OPERAND (RS2, l));
+ break;
+ case 'O':
+ switch (*++oparg)
+ {
+ case '2':
+ print (info->stream, dis_style_register, "0x%x",
+ (unsigned) EXTRACT_OPERAND (XSO2, l));
+ break;
+ case '1':
+ print (info->stream, dis_style_register, "0x%x",
+ (unsigned) EXTRACT_OPERAND (XSO1, l));
+ break;
+ }
+ break;
+ }
+ break;
default:
goto undefined_modifier;
}