diff options
Diffstat (limited to 'opcodes/aarch64-tbl.h')
| -rw-r--r-- | opcodes/aarch64-tbl.h | 133 |
1 files changed, 63 insertions, 70 deletions
diff --git a/opcodes/aarch64-tbl.h b/opcodes/aarch64-tbl.h index 71563b0..0ae7342 100644 --- a/opcodes/aarch64-tbl.h +++ b/opcodes/aarch64-tbl.h @@ -2789,12 +2789,7 @@ QLF3(V_4S, V_8H, S_H), \ } -/* Opcode table. - - Any SVE or SVE2 feature must include AARCH64_FEATURE_{SVE|SVE2} in its - bitmask, even if this is implied by other selected feature bits. This - allows verify_constraints to identify SVE instructions when selecting an - error message for MOVPRFX constraint violations. */ +/* Opcode table. */ static const aarch64_feature_set aarch64_feature_v8 = AARCH64_FEATURE (V8); @@ -2873,23 +2868,23 @@ static const aarch64_feature_set aarch64_feature_sve2 = static const aarch64_feature_set aarch64_feature_sve2aes = AARCH64_FEATURES (2, SVE_AES, SVE2_SSVE_AES); static const aarch64_feature_set aarch64_feature_sve2sha3 = - AARCH64_FEATURES (2, SVE2, SVE2_SHA3); + AARCH64_FEATURE (SVE2_SHA3); static const aarch64_feature_set aarch64_feature_sve2sm4 = - AARCH64_FEATURES (2, SVE2, SVE2_SM4); + AARCH64_FEATURE (SVE2_SM4); static const aarch64_feature_set aarch64_feature_sve2bitperm = - AARCH64_FEATURES (2, SVE2, SVE2_BITPERM); + AARCH64_FEATURE (SVE2_BITPERM); static const aarch64_feature_set aarch64_feature_sme = - AARCH64_FEATURES (2, SVE2, SME); + AARCH64_FEATURE (SME); static const aarch64_feature_set aarch64_feature_sme_f64f64 = - AARCH64_FEATURES (3, SVE2, SME, SME_F64F64); + AARCH64_FEATURE (SME_F64F64); static const aarch64_feature_set aarch64_feature_sme_i16i64 = - AARCH64_FEATURES (3, SVE2, SME, SME_I16I64); + AARCH64_FEATURE (SME_I16I64); static const aarch64_feature_set aarch64_feature_sme2 = - AARCH64_FEATURES (3, SVE2, SME, SME2); + AARCH64_FEATURE (SME2); static const aarch64_feature_set aarch64_feature_sme2_i16i64 = - AARCH64_FEATURES (2, SME2, SME_I16I64); + AARCH64_FEATURE (SME_I16I64); static const aarch64_feature_set aarch64_feature_sme2_f64f64 = - AARCH64_FEATURES (2, SME2, SME_F64F64); + AARCH64_FEATURE (SME_F64F64); static const aarch64_feature_set aarch64_feature_i8mm = AARCH64_FEATURE (I8MM); static const aarch64_feature_set aarch64_feature_i8mm_sve = @@ -2929,7 +2924,7 @@ static const aarch64_feature_set aarch64_feature_the = static const aarch64_feature_set aarch64_feature_d128_the = AARCH64_FEATURES (2, D128, THE); static const aarch64_feature_set aarch64_feature_sve_b16b16_sve2 = - AARCH64_FEATURES (2, SVE_B16B16, SVE2); + AARCH64_FEATURES (2, SVE_B16B16, SVE2_SME2); static const aarch64_feature_set aarch64_feature_sve_b16b16_sme2 = AARCH64_FEATURES (2, SVE_B16B16, SME2); static const aarch64_feature_set aarch64_feature_sme_b16b16 = @@ -2961,7 +2956,7 @@ static const aarch64_feature_set aarch64_feature_faminmax = static const aarch64_feature_set aarch64_feature_faminmax_sve2 = AARCH64_FEATURES (2, FAMINMAX, SVE2); static const aarch64_feature_set aarch64_feature_faminmax_sme2 = - AARCH64_FEATURES (3, SVE2, FAMINMAX, SME2); + AARCH64_FEATURES (2, FAMINMAX, SME2); static const aarch64_feature_set aarch64_feature_fp8 = AARCH64_FEATURE (FP8); static const aarch64_feature_set aarch64_feature_fp8_sve2 = @@ -2989,31 +2984,31 @@ static const aarch64_feature_set aarch64_feature_fp8dot4 = static const aarch64_feature_set aarch64_feature_fp8dot2 = AARCH64_FEATURE (FP8DOT2); static const aarch64_feature_set aarch64_feature_fp8fma_sve = - AARCH64_FEATURES (2, FP8FMA_SVE, SVE); + AARCH64_FEATURE (FP8FMA_SVE); static const aarch64_feature_set aarch64_feature_fp8dot4_sve = - AARCH64_FEATURES (2, FP8DOT4_SVE, SVE); + AARCH64_FEATURE (FP8DOT4_SVE); static const aarch64_feature_set aarch64_feature_fp8dot2_sve = - AARCH64_FEATURES (2, FP8DOT2_SVE, SVE); + AARCH64_FEATURE (FP8DOT2_SVE); static const aarch64_feature_set aarch64_feature_sme_f8f32 = - AARCH64_FEATURES (2, SME_F8F32, SME2); + AARCH64_FEATURE (SME_F8F32); static const aarch64_feature_set aarch64_feature_sme_f8f16 = - AARCH64_FEATURES (2, SME_F8F16, SME2); + AARCH64_FEATURE (SME_F8F16); static const aarch64_feature_set aarch64_feature_sme_f16f16_f8f16 = - AARCH64_FEATURES (2, SME_F16F16_F8F16, SME2); + AARCH64_FEATURE (SME_F16F16_F8F16); static const aarch64_feature_set aarch64_feature_sme_f16f16 = - AARCH64_FEATURES (2, SME_F16F16, SME2); + AARCH64_FEATURE (SME_F16F16); static const aarch64_feature_set aarch64_feature_sve2p1_sme = - AARCH64_FEATURES (2, SVE2p1_SME, SVE); + AARCH64_FEATURE (SVE2p1_SME); static const aarch64_feature_set aarch64_feature_sve2p1_sme2 = - AARCH64_FEATURES (2, SVE2p1_SME2, SVE); + AARCH64_FEATURE (SVE2p1_SME2); static const aarch64_feature_set aarch64_feature_sve2p1_sme2p1 = - AARCH64_FEATURES (2, SVE2p1_SME2p1, SVE); + AARCH64_FEATURE (SVE2p1_SME2p1); static const aarch64_feature_set aarch64_feature_sme2p2 = - AARCH64_FEATURES (2, SME2p2, SME); + AARCH64_FEATURE (SME2p2); static const aarch64_feature_set aarch64_feature_sve_sme2p2 = - AARCH64_FEATURES (2, SVE_SME2p2, SVE); + AARCH64_FEATURE (SVE_SME2p2); static const aarch64_feature_set aarch64_feature_sve2p2_sme2p2 = - AARCH64_FEATURES (2, SVE2p2_SME2p2, SVE); + AARCH64_FEATURE (SVE2p2_SME2p2); #define CORE &aarch64_feature_v8 #define FP &aarch64_feature_fp @@ -3126,11 +3121,11 @@ static const aarch64_feature_set aarch64_feature_sve2p2_sme2p2 = #define SVE2p2_SME2p2 &aarch64_feature_sve2p2_sme2p2 #define CORE_INSN(NAME,OPCODE,MASK,CLASS,OP,OPS,QUALS,FLAGS) \ - { NAME, OPCODE, MASK, CLASS, OP, CORE, OPS, QUALS, FLAGS, 0, 0, NULL } + { NAME, OPCODE, MASK, CLASS, OP, CORE, OPS, QUALS, FLAGS | F_INVALID_IMM_SYMS_1, 0, 0, NULL } #define __FP_INSN(NAME,OPCODE,MASK,CLASS,OP,OPS,QUALS,FLAGS) \ - { NAME, OPCODE, MASK, CLASS, OP, FP, OPS, QUALS, FLAGS, 0, 0, NULL } + { NAME, OPCODE, MASK, CLASS, OP, FP, OPS, QUALS, FLAGS | F_INVALID_IMM_SYMS_1, 0, 0, NULL } #define SIMD_INSN(NAME,OPCODE,MASK,CLASS,OP,OPS,QUALS,FLAGS) \ - { NAME, OPCODE, MASK, CLASS, OP, SIMD, OPS, QUALS, FLAGS, 0, 0, NULL } + { NAME, OPCODE, MASK, CLASS, OP, SIMD, OPS, QUALS, FLAGS | F_INVALID_IMM_SYMS_1, 0, 0, NULL } #define _SIMD_INSN(NAME,OPCODE,MASK,CLASS,OP,OPS,QUALS,FLAGS,VERIFIER) \ { NAME, OPCODE, MASK, CLASS, OP, SIMD, OPS, QUALS, FLAGS, 0, 0, VERIFIER } #define _CRC_INSN(NAME,OPCODE,MASK,CLASS,OPS,QUALS,FLAGS) \ @@ -3150,21 +3145,21 @@ static const aarch64_feature_set aarch64_feature_sve2p2_sme2p2 = #define RDMA_INSN(NAME,OPCODE,MASK,CLASS,OPS,QUALS,FLAGS) \ { NAME, OPCODE, MASK, CLASS, 0, RDMA, OPS, QUALS, FLAGS, 0, 0, NULL } #define FF16_INSN(NAME,OPCODE,MASK,CLASS,OPS,QUALS,FLAGS) \ - { NAME, OPCODE, MASK, CLASS, 0, FP_F16, OPS, QUALS, FLAGS, 0, 0, NULL } + { NAME, OPCODE, MASK, CLASS, 0, FP_F16, OPS, QUALS, FLAGS | F_INVALID_IMM_SYMS_1, 0, 0, NULL } #define SF16_INSN(NAME,OPCODE,MASK,CLASS,OPS,QUALS,FLAGS) \ - { NAME, OPCODE, MASK, CLASS, 0, SIMD_F16, OPS, QUALS, FLAGS, 0, 0, NULL } + { NAME, OPCODE, MASK, CLASS, 0, SIMD_F16, OPS, QUALS, FLAGS | F_INVALID_IMM_SYMS_1, 0, 0, NULL } #define FPRCVT_INSN(NAME,OPCODE,MASK,CLASS,OPS,QUALS,FLAGS) \ { NAME, OPCODE, MASK, CLASS, 0, FPRCVT, OPS, QUALS, FLAGS, 0, 0, NULL } #define _SVE_INSN(NAME,OPCODE,MASK,CLASS,OP,OPS,QUALS,FLAGS,TIED) \ { NAME, OPCODE, MASK, CLASS, OP, SVE, OPS, QUALS, \ - FLAGS | F_STRICT, 0, TIED, NULL } + FLAGS | F_STRICT | F_INVALID_IMM_SYMS_2, 0, TIED, NULL } #define _SVE_INSNC(NAME,OPCODE,MASK,CLASS,OP,OPS,QUALS,FLAGS,CONSTRAINTS,TIED) \ { NAME, OPCODE, MASK, CLASS, OP, SVE, OPS, QUALS, \ - FLAGS | F_STRICT, CONSTRAINTS, TIED, NULL } + FLAGS | F_STRICT | F_INVALID_IMM_SYMS_2, CONSTRAINTS, TIED, NULL } #define PAUTH_INSN(NAME,OPCODE,MASK,CLASS,OPS,QUALS,FLAGS) \ { NAME, OPCODE, MASK, CLASS, 0, PAUTH, OPS, QUALS, FLAGS, 0, 0, NULL } #define CNUM_INSN(NAME,OPCODE,MASK,CLASS,OP,OPS,QUALS,FLAGS) \ - { NAME, OPCODE, MASK, CLASS, OP, COMPNUM, OPS, QUALS, FLAGS, 0, 0, NULL } + { NAME, OPCODE, MASK, CLASS, OP, COMPNUM, OPS, QUALS, FLAGS | F_INVALID_IMM_SYMS_1, 0, 0, NULL } #define JSCVT_INSN(NAME,OPCODE,MASK,CLASS,OPS,QUALS,FLAGS) \ { NAME, OPCODE, MASK, CLASS, 0, JSCVT, OPS, QUALS, FLAGS, 0, 0, NULL } #define RCPC_INSN(NAME,OPCODE,MASK,CLASS,OPS,QUALS,FLAGS) \ @@ -3176,7 +3171,7 @@ static const aarch64_feature_set aarch64_feature_sve2p2_sme2p2 = #define AES_INSN(NAME,OPCODE,MASK,CLASS,OPS,QUALS,FLAGS) \ { NAME, OPCODE, MASK, CLASS, 0, AES, OPS, QUALS, FLAGS, 0, 0, NULL } #define SHA3_INSN(NAME,OPCODE,MASK,CLASS,OPS,QUALS,FLAGS) \ - { NAME, OPCODE, MASK, CLASS, 0, SHA3, OPS, QUALS, FLAGS, 0, 0, NULL } + { NAME, OPCODE, MASK, CLASS, 0, SHA3, OPS, QUALS, FLAGS | F_INVALID_IMM_SYMS_1, 0, 0, NULL } #define SM4_INSN(NAME,OPCODE,MASK,CLASS,OPS,QUALS,FLAGS) \ { NAME, OPCODE, MASK, CLASS, 0, SM4, OPS, QUALS, FLAGS, 0, 0, NULL } #define FP16_V8_2A_INSN(NAME,OPCODE,MASK,CLASS,OPS,QUALS,FLAGS) \ @@ -3192,30 +3187,30 @@ static const aarch64_feature_set aarch64_feature_sve2p2_sme2p2 = #define PREDRES_INSN(NAME,OPCODE,MASK,CLASS,OPS,QUALS,FLAGS) \ { NAME, OPCODE, MASK, CLASS, 0, PREDRES, OPS, QUALS, FLAGS, 0, 0, NULL } #define CMPBR_INSN(NAME,OPCODE,MASK,CLASS,OPS,QUALS,FLAGS) \ - { NAME, OPCODE, MASK, CLASS, 0, CMPBR, OPS, QUALS, FLAGS, 0, 0, NULL } + { NAME, OPCODE, MASK, CLASS, 0, CMPBR, OPS, QUALS, FLAGS | F_INVALID_IMM_SYMS_1, 0, 0, NULL } #define MEMTAG_INSN(NAME,OPCODE,MASK,CLASS,OPS,QUALS,FLAGS) \ - { NAME, OPCODE, MASK, CLASS, 0, MEMTAG, OPS, QUALS, FLAGS, 0, 0, NULL } + { NAME, OPCODE, MASK, CLASS, 0, MEMTAG, OPS, QUALS, FLAGS | F_INVALID_IMM_SYMS_1, 0, 0, NULL } #define _TME_INSN(NAME,OPCODE,MASK,CLASS,OP,OPS,QUALS,FLAGS) \ - { NAME, OPCODE, MASK, CLASS, OP, TME, OPS, QUALS, FLAGS, 0, 0, NULL } + { NAME, OPCODE, MASK, CLASS, OP, TME, OPS, QUALS, FLAGS | F_INVALID_IMM_SYMS_1, 0, 0, NULL } #define SVE2_INSN(NAME,OPCODE,MASK,CLASS,OP,OPS,QUALS,FLAGS,TIED) \ { NAME, OPCODE, MASK, CLASS, OP, SVE2, OPS, QUALS, \ - FLAGS | F_STRICT, 0, TIED, NULL } + FLAGS | F_STRICT | F_INVALID_IMM_SYMS_2, 0, TIED, NULL } #define SME2p1_INSN(NAME,OPCODE,MASK,CLASS,OP,OPS,QUALS,FLAGS,TIED) \ { NAME, OPCODE, MASK, CLASS, OP, SME2p1, OPS, QUALS, \ FLAGS | F_STRICT, 0, TIED, NULL } #define SVE_F16F32MM_INSN(NAME,OPCODE,MASK,CLASS,OP,OPS,QUALS,FLAGS) \ - { NAME, OPCODE, MASK, CLASS, OP, SVE_F16F32MM, OPS, QUALS, FLAGS, 0, 0, NULL } + { NAME, OPCODE, MASK, CLASS, OP, SVE_F16F32MM, OPS, QUALS, FLAGS | F_STRICT, 0, 0, NULL } #define F8F32MM_INSN(NAME,OPCODE,MASK,CLASS,OP,OPS,QUALS,FLAGS) \ { NAME, OPCODE, MASK, CLASS, OP, F8F32MM, OPS, QUALS, FLAGS, 0, 0, NULL } #define F8F32MM_SVE2_INSN(NAME,OPCODE,MASK,CLASS,OP,OPS,QUALS,FLAGS) \ - { NAME, OPCODE, MASK, CLASS, OP, F8F32MM_SVE2, OPS, QUALS, FLAGS, 0, 0, NULL } + { NAME, OPCODE, MASK, CLASS, OP, F8F32MM_SVE2, OPS, QUALS, FLAGS | F_STRICT, 0, 0, NULL } #define F8F16MM_INSN(NAME,OPCODE,MASK,CLASS,OP,OPS,QUALS,FLAGS) \ { NAME, OPCODE, MASK, CLASS, OP, F8F16MM, OPS, QUALS, FLAGS, 0, 0, NULL } #define F8F16MM_SVE2_INSN(NAME,OPCODE,MASK,CLASS,OP,OPS,QUALS,FLAGS) \ - { NAME, OPCODE, MASK, CLASS, OP, F8F16MM_SVE2, OPS, QUALS, FLAGS, 0, 0, NULL } + { NAME, OPCODE, MASK, CLASS, OP, F8F16MM_SVE2, OPS, QUALS, FLAGS | F_STRICT, 0, 0, NULL } #define SVE2_INSNC(NAME,OPCODE,MASK,CLASS,OP,OPS,QUALS,FLAGS,CONSTRAINTS,TIED) \ { NAME, OPCODE, MASK, CLASS, OP, SVE2, OPS, QUALS, \ - FLAGS | F_STRICT, CONSTRAINTS, TIED, NULL } + FLAGS | F_STRICT | F_INVALID_IMM_SYMS_2, CONSTRAINTS, TIED, NULL } #define B16B16_SVE2_INSN(NAME,OPCODE,MASK,CLASS,OP,OPS,QUALS,FLAGS,TIED) \ { NAME, OPCODE, MASK, CLASS, OP, B16B16_SVE2, OPS, QUALS, \ FLAGS | F_STRICT, 0, TIED, NULL } @@ -3254,7 +3249,7 @@ static const aarch64_feature_set aarch64_feature_sve2p2_sme2p2 = FLAGS | F_STRICT, CONSTRAINTS, TIED, NULL } #define SME_INSN(NAME,OPCODE,MASK,CLASS,OP,OPS,QUALS,FLAGS,TIED) \ { NAME, OPCODE, MASK, CLASS, OP, SME, OPS, QUALS, \ - F_STRICT | FLAGS, 0, TIED, NULL } + F_STRICT | F_INVALID_IMM_SYMS_2 | FLAGS, 0, TIED, NULL } #define SME_F64F64_INSN(NAME,OPCODE,MASK,CLASS,OP,OPS,QUALS,FLAGS,TIED) \ { NAME, OPCODE, MASK, CLASS, OP, SME_F64F64, OPS, QUALS, \ F_STRICT | FLAGS, 0, TIED, NULL } @@ -3266,7 +3261,7 @@ static const aarch64_feature_set aarch64_feature_sve2p2_sme2p2 = F_STRICT | FLAGS, CONSTRAINTS, TIED, NULL } #define SME2_INSN(NAME,OPCODE,MASK,CLASS,OP,OPS,QUALS,FLAGS,TIED) \ { NAME, OPCODE, MASK, CLASS, OP, SME2, OPS, QUALS, \ - F_STRICT | FLAGS, 0, TIED, NULL } + F_STRICT | F_INVALID_IMM_SYMS_3 | FLAGS, 0, TIED, NULL } #define SME2_INSNC(NAME,OPCODE,MASK,CLASS,OP,OPS,QUALS,FLAGS,CONSTRAINTS,TIED) \ { NAME, OPCODE, MASK, CLASS, OP, SME2, OPS, QUALS, \ FLAGS | F_STRICT, CONSTRAINTS, TIED, NULL } @@ -3280,36 +3275,34 @@ static const aarch64_feature_set aarch64_feature_sve2p2_sme2p2 = { NAME, OPCODE, MASK, CLASS, OP, SVE2_BITPERM, OPS, QUALS, \ FLAGS | F_STRICT, 0, TIED, NULL } #define SVE_BFSCALE_INSN(NAME,OPCODE,MASK,CLASS,OPS,QUALS,FLAGS,TIED) \ - { NAME, OPCODE, MASK, CLASS, 0, SVE_BFSCALE, OPS, QUALS, FLAGS, 0, TIED, NULL } + { NAME, OPCODE, MASK, CLASS, 0, SVE_BFSCALE, OPS, QUALS, FLAGS | F_STRICT, 0, TIED, NULL } #define SVE_BFSCALE_SME2_INSN(NAME,OPCODE,MASK,CLASS,OPS,QUALS,FLAGS,TIED) \ - { NAME, OPCODE, MASK, CLASS, 0, SVE_BFSCALE_SME2, OPS, QUALS, FLAGS, 0, TIED, NULL } -#define BFLOAT16_SVE_INSN(NAME,OPCODE,MASK,CLASS,OPS,QUALS,FLAGS) \ - { NAME, OPCODE, MASK, CLASS, 0, BFLOAT16_SVE, OPS, QUALS, FLAGS, 0, 0, NULL } + { NAME, OPCODE, MASK, CLASS, 0, SVE_BFSCALE_SME2, OPS, QUALS, FLAGS | F_STRICT, 0, TIED, NULL } #define BFLOAT16_SVE_INSNC(NAME,OPCODE,MASK,CLASS,OPS,QUALS,FLAGS, CONSTRAINTS, TIED) \ { NAME, OPCODE, MASK, CLASS, 0, BFLOAT16_SVE, OPS, QUALS, FLAGS | F_STRICT, \ CONSTRAINTS, TIED, NULL } #define BFLOAT16_INSN(NAME,OPCODE,MASK,CLASS,OPS,QUALS,FLAGS) \ { NAME, OPCODE, MASK, CLASS, 0, BFLOAT16, OPS, QUALS, FLAGS, 0, 0, NULL } #define INT8MATMUL_SVE_INSNC(NAME,OPCODE,MASK,CLASS,OPS,QUALS,FLAGS, CONSTRAINTS, TIED) \ - { NAME, OPCODE, MASK, CLASS, 0, I8MM_SVE, OPS, QUALS, FLAGS, CONSTRAINTS, TIED, NULL } + { NAME, OPCODE, MASK, CLASS, 0, I8MM_SVE, OPS, QUALS, FLAGS | F_STRICT, CONSTRAINTS, TIED, NULL } #define INT8MATMUL_INSN(NAME,OPCODE,MASK,CLASS,OPS,QUALS,FLAGS) \ { NAME, OPCODE, MASK, CLASS, 0, I8MM, OPS, QUALS, FLAGS, 0, 0, NULL } #define F64MATMUL_SVE_INSN(NAME,OPCODE,MASK,CLASS,OPS,QUALS,FLAGS,TIED) \ - { NAME, OPCODE, MASK, CLASS, 0, F64MM_SVE, OPS, QUALS, FLAGS, 0, TIED, NULL } + { NAME, OPCODE, MASK, CLASS, 0, F64MM_SVE, OPS, QUALS, FLAGS | F_STRICT, 0, TIED, NULL } #define F64MATMUL_SVE_INSNC(NAME,OPCODE,MASK,CLASS,OPS,QUALS,FLAGS, CONSTRAINTS, TIED) \ - { NAME, OPCODE, MASK, CLASS, 0, F64MM_SVE, OPS, QUALS, FLAGS, CONSTRAINTS, TIED, NULL } + { NAME, OPCODE, MASK, CLASS, 0, F64MM_SVE, OPS, QUALS, FLAGS | F_STRICT, CONSTRAINTS, TIED, NULL } #define F32MATMUL_SVE_INSNC(NAME,OPCODE,MASK,CLASS,OPS,QUALS,FLAGS, CONSTRAINTS, TIED) \ - { NAME, OPCODE, MASK, CLASS, 0, F32MM_SVE, OPS, QUALS, FLAGS, CONSTRAINTS, TIED, NULL } + { NAME, OPCODE, MASK, CLASS, 0, F32MM_SVE, OPS, QUALS, FLAGS | F_STRICT, CONSTRAINTS, TIED, NULL } #define V8R_INSN(NAME,OPCODE,MASK,CLASS,OPS,QUALS,FLAGS) \ { NAME, OPCODE, MASK, CLASS, 0, ARMV8R, OPS, QUALS, FLAGS, 0, 0, NULL } #define XS_INSN(NAME,OPCODE,MASK,CLASS,OPS,QUALS,FLAGS) \ - { NAME, OPCODE, MASK, CLASS, 0, XS, OPS, QUALS, FLAGS, 0, 0, NULL } + { NAME, OPCODE, MASK, CLASS, 0, XS, OPS, QUALS, FLAGS | F_INVALID_IMM_SYMS_1, 0, 0, NULL } #define WFXT_INSN(NAME,OPCODE,MASK,CLASS,OPS,QUALS,FLAGS) \ { NAME, OPCODE, MASK, CLASS, 0, WFXT, OPS, QUALS, FLAGS, 0, 0, NULL } #define _LS64_INSN(NAME,OPCODE,MASK,CLASS,OPS,QUALS,FLAGS) \ { NAME, OPCODE, MASK, CLASS, 0, LS64, OPS, QUALS, FLAGS, 0, 0, NULL } #define FLAGM_INSN(NAME,OPCODE,MASK,CLASS,OPS,QUALS,FLAGS) \ - { NAME, OPCODE, MASK, CLASS, 0, FLAGM, OPS, QUALS, FLAGS, 0, 0, NULL } + { NAME, OPCODE, MASK, CLASS, 0, FLAGM, OPS, QUALS, FLAGS | F_INVALID_IMM_SYMS_1, 0, 0, NULL } #define MOPS_INSN(NAME, OPCODE, MASK, CLASS, OPS, QUALS, FLAGS, CONSTRAINTS, VERIFIER) \ { NAME, OPCODE, MASK, CLASS, 0, MOPS, OPS, QUALS, FLAGS, CONSTRAINTS, \ 0, VERIFIER } @@ -3319,13 +3312,13 @@ static const aarch64_feature_set aarch64_feature_sve2p2_sme2p2 = #define HBC_INSN(NAME,OPCODE,MASK,CLASS,OPS,QUALS,FLAGS) \ { NAME, OPCODE, MASK, CLASS, 0, HBC, OPS, QUALS, FLAGS, 0, 0, NULL } #define CSSC_INSN(NAME,OPCODE,MASK,OPS,QUALS,FLAGS) \ - { NAME, OPCODE, MASK, cssc, 0, CSSC, OPS, QUALS, FLAGS, 0, 0, NULL } + { NAME, OPCODE, MASK, cssc, 0, CSSC, OPS, QUALS, FLAGS | F_INVALID_IMM_SYMS_1, 0, 0, NULL } #define CHK_INSN(NAME, OPCODE, MASK, OPS, QUALS, FLAGS) \ { NAME, OPCODE, MASK, ic_system, 0, CHK, OPS, QUALS, FLAGS, 0, 0, NULL } #define GCS_INSN(NAME, OPCODE, MASK, OPS, QUALS, FLAGS) \ { NAME, OPCODE, MASK, gcs, 0, GCS, OPS, QUALS, FLAGS, 0, 0, NULL } #define D128_INSN(NAME,OPCODE,MASK,OPS,QUALS,FLAGS) \ - { NAME, OPCODE, MASK, ic_system, 0, D128, OPS, QUALS, FLAGS, 0, 0, NULL } + { NAME, OPCODE, MASK, ic_system, 0, D128, OPS, QUALS, FLAGS | F_INVALID_IMM_SYMS_1, 0, 0, NULL } #define THE_INSN(NAME,OPCODE,MASK,OPS,QUALS,FLAGS) \ { NAME, OPCODE, MASK, the, 0, THE, OPS, QUALS, FLAGS, 0, 0, NULL } #define D128_THE_INSN(NAME,OPCODE,MASK,OPS,QUALS,FLAGS) \ @@ -3341,10 +3334,10 @@ static const aarch64_feature_set aarch64_feature_sve2p2_sme2p2 = { NAME, OPCODE, MASK, asimdsame, 0, FAMINMAX, OPS, QUALS, FLAGS, 0, 0, NULL } #define FAMINMAX_SVE2_INSN(NAME,OPCODE,MASK,OPS,QUALS,CONSTRAINTS) \ { NAME, OPCODE, MASK, sve_size_hsd, 0, FAMINMAX_SVE2, OPS, QUALS, \ - 0 | F_STRICT, CONSTRAINTS, 2, NULL } + F_STRICT, CONSTRAINTS, 2, NULL } #define FAMINMAX_SME2_INSN(NAME,OPCODE,MASK,OPS,QUALS) \ { NAME, OPCODE, MASK, sme_size_22_hsd, 0, FAMINMAX_SME2, OPS, QUALS, \ - F_STRICT | 0, 0, 1, NULL } + F_STRICT, 0, 1, NULL } #define FP8_INSN(NAME, OPCODE, MASK, CLASS, OPS, QUALS, FLAGS) \ { NAME, OPCODE, MASK, CLASS, 0, FP8, OPS, QUALS, FLAGS, 0, 0, NULL } #define FP8_SVE2_INSN(NAME,OPCODE,MASK,CLASS,OP,OPS,QUALS,FLAGS,TIED) \ @@ -3356,16 +3349,16 @@ static const aarch64_feature_set aarch64_feature_sve2p2_sme2p2 = #define LUT_INSN(NAME,OPCODE,MASK,OPS,QUALS,FLAGS) \ { NAME, OPCODE, MASK, lut, 0, LUT, OPS, QUALS, FLAGS, 0, 0, NULL } #define LUT_SVE2_INSN(NAME,OPCODE,MASK,OPS,QUALS,FLAGS,CONSTRAINTS) \ - { NAME, OPCODE, MASK, lut, 0, LUT_SVE2, OPS, QUALS, \ - FLAGS, CONSTRAINTS, 0, NULL } + { NAME, OPCODE, MASK, sve_misc, 0, LUT_SVE2, OPS, QUALS, \ + FLAGS | F_STRICT, CONSTRAINTS, 0, NULL } #define BRBE_INSN(NAME,OPCODE,MASK,OPS,QUALS,FLAGS) \ { NAME, OPCODE, MASK, ic_system, 0, BRBE, OPS, QUALS, FLAGS, 0, 0, NULL } #define LUTv2_SME2_INSN(NAME,OPCODE,MASK,CLASS,OPS,QUALS,FLAGS) \ { NAME, OPCODE, MASK, CLASS, 0, LUTv2_SME2, OPS, QUALS, \ - FLAGS, 0, 0, NULL } + FLAGS | F_STRICT, 0, 0, NULL } #define LUTv2_SME2p1_INSN(NAME,OPCODE,MASK,CLASS,OPS,QUALS,FLAGS) \ { NAME, OPCODE, MASK, CLASS, 0, LUTv2_SME2p1, OPS, QUALS, \ - FLAGS, 0, 0, NULL } + FLAGS | F_STRICT, 0, 0, NULL } #define FP8FMA_INSN(NAME,OPCODE,MASK,CLASS,OPS,QUALS,FLAGS) \ { NAME, OPCODE, MASK, CLASS, 0, FP8FMA, OPS, QUALS, FLAGS, 0, 0, NULL } #define FP8DOT4_INSN(NAME,OPCODE,MASK,CLASS,OPS,QUALS,FLAGS) \ @@ -3395,7 +3388,7 @@ static const aarch64_feature_set aarch64_feature_sve2p2_sme2p2 = F_STRICT | FLAGS, CONSTRAINTS, TIED, NULL } #define SVE2p1_SME2_INSN(NAME,OPCODE,MASK,CLASS,OP,OPS,QUALS,FLAGS,TIED) \ { NAME, OPCODE, MASK, CLASS, OP, SVE2p1_SME2, OPS, QUALS, \ - F_STRICT | FLAGS, 0, TIED, NULL } + F_STRICT | F_INVALID_IMM_SYMS_2 | FLAGS, 0, TIED, NULL } #define SVE2p1_SME2_INSNC(NAME,OPCODE,MASK,CLASS,OP,OPS,QUALS,FLAGS,CONSTRAINTS,TIED) \ { NAME, OPCODE, MASK, CLASS, OP, SVE2p1_SME2, OPS, QUALS, \ F_STRICT | FLAGS, CONSTRAINTS, TIED, NULL } @@ -3404,7 +3397,7 @@ static const aarch64_feature_set aarch64_feature_sve2p2_sme2p2 = F_STRICT | FLAGS, 0, TIED, NULL } #define SVE2p1_SME2p1_INSNC(NAME,OPCODE,MASK,CLASS,OP,OPS,QUALS,FLAGS,CONSTRAINTS,TIED) \ { NAME, OPCODE, MASK, CLASS, OP, SVE2p1_SME2p1, OPS, QUALS, \ - F_STRICT | FLAGS, CONSTRAINTS, TIED, NULL } + F_STRICT | F_INVALID_IMM_SYMS_2 | FLAGS, CONSTRAINTS, TIED, NULL } #define SVE_SME2p2_INSN(NAME,OPCODE,MASK,CLASS,OP,OPS,QUALS,FLAGS,TIED) \ { NAME, OPCODE, MASK, CLASS, OP, SVE_SME2p2, OPS, QUALS, \ FLAGS | F_STRICT, 0, TIED, NULL } @@ -8206,7 +8199,7 @@ const struct aarch64_opcode aarch64_opcode_table[] = "a register destination address with writeback") \ Y(INT_REG, x0_to_x30, "MOPS_ADDR_Rs", 0, F(FLD_Rs), \ "a register source address with writeback") \ - Y(INT_REG, x0_to_x30, "MOPS_WB_Rd", 0, F(FLD_Rn), \ + Y(INT_REG, x0_to_x30, "MOPS_WB_Rn", 0, F(FLD_Rn), \ "an integer register with writeback") \ Y(IMMEDIATE, imm, "CSSC_SIMM8", OPD_F_SEXT, F(FLD_CSSC_imm8), \ "an 8-bit signed immediate") \ |