diff options
| -rw-r--r-- | bfd/ChangeLog | 5 | ||||
| -rw-r--r-- | bfd/elfxx-mips.c | 8 | ||||
| -rw-r--r-- | gas/ChangeLog | 6 | ||||
| -rw-r--r-- | gas/config/tc-mips.c | 3 | ||||
| -rw-r--r-- | include/opcode/ChangeLog | 5 | ||||
| -rw-r--r-- | include/opcode/mips.h | 4 |
6 files changed, 23 insertions, 8 deletions
diff --git a/bfd/ChangeLog b/bfd/ChangeLog index 8839ea0..99ada02 100644 --- a/bfd/ChangeLog +++ b/bfd/ChangeLog @@ -1,3 +1,8 @@ +2010-11-23 Mingming Sun <mingm.sun@gmail.com> + + * elfxx-mips.c (mips_set_isa_flags): Move bfd_mach_loongson_3a + after bfd_mach_mips_sb1. + 2010-11-17 Tristan Gingold <gingold@adacore.com> * vms-lib.c (vms_write_index): Add comments. diff --git a/bfd/elfxx-mips.c b/bfd/elfxx-mips.c index cfbb06e..dcf6a9e 100644 --- a/bfd/elfxx-mips.c +++ b/bfd/elfxx-mips.c @@ -10559,14 +10559,14 @@ mips_set_isa_flags (bfd *abfd) val = E_MIPS_ARCH_3 | E_MIPS_MACH_LS2F; break; - case bfd_mach_mips_loongson_3a: - val = E_MIPS_ARCH_64 | E_MIPS_MACH_LS3A; - break; - case bfd_mach_mips_sb1: val = E_MIPS_ARCH_64 | E_MIPS_MACH_SB1; break; + case bfd_mach_mips_loongson_3a: + val = E_MIPS_ARCH_64 | E_MIPS_MACH_LS3A; + break; + case bfd_mach_mips_octeon: val = E_MIPS_ARCH_64R2 | E_MIPS_MACH_OCTEON; break; diff --git a/gas/ChangeLog b/gas/ChangeLog index 7b00c40..b5e005a 100644 --- a/gas/ChangeLog +++ b/gas/ChangeLog @@ -1,6 +1,10 @@ +2010-11-23 Mingming Sun <mingm.sun@gmail.com> + + * config/tc-mips.c (mips_cpu_info_table): Move loongson3a after sb1. + 2010-11-23 H.J. Lu <hongjiu.lu@intel.com> - * doc/as.texinfo: Refer to and include c-i386.texi for i386 + * doc/as.texinfo: Refer to and include c-i386.texi for i386 options. * doc/c-i386.texi: Add markup for use in manpage generation. diff --git a/gas/config/tc-mips.c b/gas/config/tc-mips.c index 77397bb..ac02aee 100644 --- a/gas/config/tc-mips.c +++ b/gas/config/tc-mips.c @@ -15358,7 +15358,6 @@ static const struct mips_cpu_info mips_cpu_info_table[] = { "5kf", 0, ISA_MIPS64, CPU_MIPS64 }, { "20kc", MIPS_CPU_ASE_MIPS3D, ISA_MIPS64, CPU_MIPS64 }, { "25kf", MIPS_CPU_ASE_MIPS3D, ISA_MIPS64, CPU_MIPS64 }, - { "loongson3a", 0, ISA_MIPS64, CPU_LOONGSON_3A }, /* Broadcom SB-1 CPU core */ { "sb1", MIPS_CPU_ASE_MIPS3D | MIPS_CPU_ASE_MDMX, @@ -15366,6 +15365,8 @@ static const struct mips_cpu_info mips_cpu_info_table[] = /* Broadcom SB-1A CPU core */ { "sb1a", MIPS_CPU_ASE_MIPS3D | MIPS_CPU_ASE_MDMX, ISA_MIPS64, CPU_SB1 }, + + { "loongson3a", 0, ISA_MIPS64, CPU_LOONGSON_3A }, /* MIPS 64 Release 2 */ diff --git a/include/opcode/ChangeLog b/include/opcode/ChangeLog index 197220d..8ea9b98 100644 --- a/include/opcode/ChangeLog +++ b/include/opcode/ChangeLog @@ -1,3 +1,8 @@ +2010-11-23 Maciej W. Rozycki <macro@linux-mips.org> + + * mips.h (INSN_CHIP_MASK): Update according to INSN_LOONGSON_3A. + (INSN_LOONGSON_3A): Clear bit 31. + 2010-11-15 Matthew Gretton-Dann <matthew.gretton-dann@arm.com> PR gas/12198 diff --git a/include/opcode/mips.h b/include/opcode/mips.h index 8817ce3..af9ad21 100644 --- a/include/opcode/mips.h +++ b/include/opcode/mips.h @@ -544,7 +544,7 @@ static const unsigned int mips_isa_table[] = { 0x0001, 0x0003, 0x0607, 0x1e0f, 0x3e1f, 0x0a23, 0x3e63, 0x3ebf, 0x3fff }; /* Masks used for Chip specific instructions. */ -#define INSN_CHIP_MASK 0xc3ff0820 +#define INSN_CHIP_MASK 0xc3ff0c20 /* Cavium Networks Octeon instructions. */ #define INSN_OCTEON 0x00000800 @@ -593,7 +593,7 @@ static const unsigned int mips_isa_table[] = /* ST Microelectronics Loongson 2E. */ #define INSN_LOONGSON_2E 0x40000000 /* ST Microelectronics Loongson 2F. */ -#define INSN_LOONGSON_2F 0x80000000 +#define INSN_LOONGSON_3A 0x00000400 /* Loongson 3A. */ #define INSN_LOONGSON_3A 0x80000400 /* RMI Xlr instruction */ |