diff options
| -rw-r--r-- | binutils/ChangeLog | 4 | ||||
| -rw-r--r-- | binutils/od-macho.c | 2 | ||||
| -rw-r--r-- | cpu/ChangeLog | 4 | ||||
| -rw-r--r-- | cpu/or1kcommon.cpu | 2 | ||||
| -rw-r--r-- | include/ChangeLog | 7 | ||||
| -rw-r--r-- | include/mach-o/unwind.h | 4 | ||||
| -rw-r--r-- | opcodes/ChangeLog | 5 | ||||
| -rw-r--r-- | opcodes/cr16-opc.c | 2 | ||||
| -rw-r--r-- | opcodes/hppa-dis.c | 2 | ||||
| -rw-r--r-- | sim/ppc/ChangeLog | 5 | ||||
| -rw-r--r-- | sim/ppc/e500_registers.h | 2 | ||||
| -rw-r--r-- | sim/ppc/ppc-instructions | 2 |
12 files changed, 33 insertions, 8 deletions
diff --git a/binutils/ChangeLog b/binutils/ChangeLog index d2d2553..4cc4cba 100644 --- a/binutils/ChangeLog +++ b/binutils/ChangeLog @@ -1,3 +1,7 @@ +2018-05-09 Sebastian Rasmussen <sebras@gmail.com> + + * od-macho.c (dump_unwind_encoding_x86): Adjust for macro renaming. + 2018-05-08 Alan Modra <amodra@gmail.com> PR 23141 diff --git a/binutils/od-macho.c b/binutils/od-macho.c index fb2ed70..b0c39b3 100644 --- a/binutils/od-macho.c +++ b/binutils/od-macho.c @@ -1688,7 +1688,7 @@ dump_unwind_encoding_x86 (unsigned int encoding, unsigned int sz, unsigned int regs; char pfx = sz == 8 ? 'R' : 'E'; - regs = encoding & MACH_O_UNWIND_X86_64_RBP_FRAME_REGSITERS; + regs = encoding & MACH_O_UNWIND_X86_64_RBP_FRAME_REGISTERS printf (" %cSP frame", pfx); if (regs != 0) { diff --git a/cpu/ChangeLog b/cpu/ChangeLog index 5581d87..affb4d7 100644 --- a/cpu/ChangeLog +++ b/cpu/ChangeLog @@ -1,3 +1,7 @@ +2018-05-09 Sebastian Rasmussen <sebras@gmail.com> + + * or1kcommon.cpu (spr-reg-info): Typo fix. + 2018-03-03 Alan Modra <amodra@gmail.com> * frv.opc: Include opintl.h. diff --git a/cpu/or1kcommon.cpu b/cpu/or1kcommon.cpu index ced70c3..86d440c 100644 --- a/cpu/or1kcommon.cpu +++ b/cpu/or1kcommon.cpu @@ -170,7 +170,7 @@ (SYS DCFGR #x007 "Debug configuration register") (SYS PCCFGR #x008 "Performance counters configuration register") (SYS NPC #x010 "Next program counter") - (SYS SR #x011 "Supervision Regsiter") + (SYS SR #x011 "Supervision Register") (SYS PPC #x012 "Previous program counter") (SYS FPCSR #x014 "Floating point control status register") (.unsplice diff --git a/include/ChangeLog b/include/ChangeLog index 5dceeb1..3e74a76 100644 --- a/include/ChangeLog +++ b/include/ChangeLog @@ -1,3 +1,10 @@ +2018-05-09 Sebastian Rasmussen <sebras@gmail.com> + + * mach-o/unwind.h (MACH_O_UNWIND_X86_64_RBP_FRAME_REGISTERS): + Rename from MACH_O_UNWIND_X86_64_RBP_FRAME_REGSITERS. + (MACH_O_UNWIND_X86_EBP_FRAME_REGISTERS): Rename from + MACH_O_UNWIND_X86_EBP_FRAME_REGSITERS. + 2018-05-08 Jim Wilson <jimw@sifive.com> * opcode/riscv-opc.h (MATCH_C_SRLI64, MASK_C_SRLI64): New. diff --git a/include/mach-o/unwind.h b/include/mach-o/unwind.h index da64c16..d95dc98 100644 --- a/include/mach-o/unwind.h +++ b/include/mach-o/unwind.h @@ -37,7 +37,7 @@ %rbp-2040 (offset is encoded in offset bits * 8). Registers saved are encoded in registers bits, 3 bits per register. */ #define MACH_O_UNWIND_X86_64_MODE_RBP_FRAME 0x01000000 -#define MACH_O_UNWIND_X86_64_RBP_FRAME_REGSITERS 0x00007FFF +#define MACH_O_UNWIND_X86_64_RBP_FRAME_REGISTERS 0x00007FFF #define MACH_O_UNWIND_X86_64_RBP_FRAME_OFFSET 0x00FF0000 /* Frameless function, with a small stack size. */ @@ -75,7 +75,7 @@ %ebp-240 (offset is encoded in offset bits * 4). Registers saved are encoded in registers bits, 3 bits per register. */ #define MACH_O_UNWIND_X86_MODE_EBP_FRAME 0x01000000 -#define MACH_O_UNWIND_X86_EBP_FRAME_REGSITERS 0x00007FFF +#define MACH_O_UNWIND_X86_EBP_FRAME_REGISTERS 0x00007FFF #define MACH_O_UNWIND_X86_EBP_FRAME_OFFSET 0x00FF0000 /* Frameless function, with a small stack size. */ diff --git a/opcodes/ChangeLog b/opcodes/ChangeLog index 277bfb1..4dfd501 100644 --- a/opcodes/ChangeLog +++ b/opcodes/ChangeLog @@ -1,3 +1,8 @@ +2018-05-09 Sebastian Rasmussen <sebras@gmail.com> + + * cr16-opc.c (cr16_instruction): Comment typo fix. + * hppa-dis.c (print_insn_hppa): Likewise. + 2018-05-08 Jim Wilson <jimw@sifive.com> * riscv-opc.c (match_c_slli, match_slli_as_c_slli): New. diff --git a/opcodes/cr16-opc.c b/opcodes/cr16-opc.c index 1875379..b477dbe 100644 --- a/opcodes/cr16-opc.c +++ b/opcodes/cr16-opc.c @@ -276,7 +276,7 @@ const inst cr16_instruction[] = {"storm", 1, 0x16, 19, NO_TYPE_INS | REG_LIST, {{uimm3_1,16}}}, {"stormp", 1, 0x17, 19, NO_TYPE_INS | REG_LIST, {{uimm3_1,16}}}, - /* Processor Regsiter Manipulation instructions */ + /* Processor Register Manipulation instructions */ /* opc16 reg, preg */ {"lpr", 2, 0x00140, 12, NO_TYPE_INS, {{regr,0}, {pregr,4}}}, /* opc16 regp, pregp */ diff --git a/opcodes/hppa-dis.c b/opcodes/hppa-dis.c index 48003dc..3658eec 100644 --- a/opcodes/hppa-dis.c +++ b/opcodes/hppa-dis.c @@ -425,7 +425,7 @@ print_insn_hppa (bfd_vma memaddr, disassemble_info *info) fput_fp_reg (GET_FIELD (insn, 6, 10), info); break; - /* 'fA' will not generate a space before the regsiter + /* 'fA' will not generate a space before the register name. Normally that is fine. Except that it causes problems with xmpyu which has no FP format completer. */ diff --git a/sim/ppc/ChangeLog b/sim/ppc/ChangeLog index 9573e7b..8ecdab8 100644 --- a/sim/ppc/ChangeLog +++ b/sim/ppc/ChangeLog @@ -1,3 +1,8 @@ +2018-05-09 Sebastian Rasmussen <sebras@gmail.com> + + * e500_registers.h: Comment typo fix. + * ppc-instructions (ppc_insn_mfcr): Likewise. + 2017-09-05 John Baldwin <jhb@FreeBSD.org> PR sim/20863 diff --git a/sim/ppc/e500_registers.h b/sim/ppc/e500_registers.h index c06a88f..ee58635 100644 --- a/sim/ppc/e500_registers.h +++ b/sim/ppc/e500_registers.h @@ -28,7 +28,7 @@ enum { msr_e500_spu_enable = BIT(38) }; -/* E500 regsiters. */ +/* E500 registers. */ enum { diff --git a/sim/ppc/ppc-instructions b/sim/ppc/ppc-instructions index 5e6d21d..9f97734 100644 --- a/sim/ppc/ppc-instructions +++ b/sim/ppc/ppc-instructions @@ -734,7 +734,7 @@ void::model-function::ppc_insn_to_spr:itable_index index, model_data *model_ptr, busy_ptr->nr_writebacks = 1; TRACE(trace_model,("Making register %s busy.\n", spr_name(nSPR))); -# Schedule a MFCR instruction that moves the CR into an integer regsiter +# Schedule a MFCR instruction that moves the CR into an integer register void::model-function::ppc_insn_mfcr:itable_index index, model_data *model_ptr, unsigned32 int_mask const unsigned32 cr_mask = 0xff; model_busy *busy_ptr; |