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-rw-r--r--gas/ChangeLog6
-rw-r--r--gas/config/tc-aarch64.c10
-rw-r--r--gas/testsuite/gas/aarch64/dotproduct.d864
-rw-r--r--include/ChangeLog5
-rw-r--r--include/opcode/aarch64.h5
-rw-r--r--opcodes/ChangeLog10
-rw-r--r--opcodes/aarch64-asm.c2
-rw-r--r--opcodes/aarch64-dis.c2
-rw-r--r--opcodes/aarch64-opc.c1
-rw-r--r--opcodes/aarch64-tbl.h4
10 files changed, 471 insertions, 438 deletions
diff --git a/gas/ChangeLog b/gas/ChangeLog
index 608d39b..525f771 100644
--- a/gas/ChangeLog
+++ b/gas/ChangeLog
@@ -1,5 +1,11 @@
2017-12-19 Tamar Christina <tamar.christina@arm.com>
+ PR 22559
+ * config/tc-aarch64.c (vectype_to_qualifier): Support AARCH64_OPND_QLF_S_4B.
+ * gas/testsuite/gas/aarch64/dotproduct.d: Update disassembly.
+
+2017-12-19 Tamar Christina <tamar.christina@arm.com>
+
PR 22529
* config/tc-aarch64.c (vectype_to_qualifier): Support AARCH64_OPND_QLF_V_4B.
* gas/testsuite/gas/aarch64/pr22529.s: New.
diff --git a/gas/config/tc-aarch64.c b/gas/config/tc-aarch64.c
index 6b5179e..9e2cd50 100644
--- a/gas/config/tc-aarch64.c
+++ b/gas/config/tc-aarch64.c
@@ -4929,8 +4929,14 @@ vectype_to_qualifier (const struct vector_type_el *vectype)
gas_assert (vectype->type >= NT_b && vectype->type <= NT_q);
if (vectype->defined & (NTA_HASINDEX | NTA_HASVARWIDTH))
- /* Vector element register. */
- return AARCH64_OPND_QLF_S_B + vectype->type;
+ {
+ /* Special case S_4B. */
+ if (vectype->type == NT_b && vectype->width == 4)
+ return AARCH64_OPND_QLF_S_4B;
+
+ /* Vector element register. */
+ return AARCH64_OPND_QLF_S_B + vectype->type;
+ }
else
{
/* Vector register. */
diff --git a/gas/testsuite/gas/aarch64/dotproduct.d b/gas/testsuite/gas/aarch64/dotproduct.d
index 58669ff..54ac62b 100644
--- a/gas/testsuite/gas/aarch64/dotproduct.d
+++ b/gas/testsuite/gas/aarch64/dotproduct.d
@@ -114,435 +114,435 @@ Disassembly of section \.text:
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[^:]+:\s+4e9696d6 sdot v22.4s, v22.16b, v22.16b
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diff --git a/include/ChangeLog b/include/ChangeLog
index ecfd766..144c138 100644
--- a/include/ChangeLog
+++ b/include/ChangeLog
@@ -1,5 +1,10 @@
2017-12-19 Tamar Christina <tamar.christina@arm.com>
+ PR gas/22559
+ * aarch64.h (aarch64_opnd_qualifier): Add AARCH64_OPND_QLF_S_4B.
+
+2017-12-19 Tamar Christina <tamar.christina@arm.com>
+
PR gas/22529
* opcode/aarch64.h (aarch64_opnd_qualifier): Add AARCH64_OPND_QLF_V_4B.
diff --git a/include/opcode/aarch64.h b/include/opcode/aarch64.h
index 453b177..1ebc492 100644
--- a/include/opcode/aarch64.h
+++ b/include/opcode/aarch64.h
@@ -396,6 +396,11 @@ enum aarch64_opnd_qualifier
AARCH64_OPND_QLF_S_S,
AARCH64_OPND_QLF_S_D,
AARCH64_OPND_QLF_S_Q,
+ /* This type qualifier has a special meaning in that it means that 4 x 1 byte
+ are selected by the instruction. Other than that it has no difference
+ with AARCH64_OPND_QLF_S_B in encoding. It is here purely for syntactical
+ reasons and is an exception from normal AArch64 disassembly scheme. */
+ AARCH64_OPND_QLF_S_4B,
/* Qualifying an operand which is a SIMD vector register or a SIMD vector
register list; indicating register shape.
diff --git a/opcodes/ChangeLog b/opcodes/ChangeLog
index a8b8dba..aa31dd3 100644
--- a/opcodes/ChangeLog
+++ b/opcodes/ChangeLog
@@ -1,5 +1,15 @@
2017-12-19 Tamar Christina <tamar.christina@arm.com>
+ PR gas/22559
+ * aarch64-asm.c (aarch64_ins_reglane): Change AARCH64_OPND_QLF_S_B to
+ AARCH64_OPND_QLF_S_4B
+ * aarch64-dis.c (aarch64_ext_reglane): Change AARCH64_OPND_QLF_S_B to
+ AARCH64_OPND_QLF_S_4B
+ * aarch64-opc.c (aarch64_opnd_qualifiers): Add 4b variant.
+ * aarch64-tbl.h (QL_V2DOT): Change S_B to S_4B.
+
+2017-12-19 Tamar Christina <tamar.christina@arm.com>
+
PR gas/22529
* aarch64-opc.c (aarch64_opnd_qualifiers): Add 4b variant.
diff --git a/opcodes/aarch64-asm.c b/opcodes/aarch64-asm.c
index 9294910..92de737 100644
--- a/opcodes/aarch64-asm.c
+++ b/opcodes/aarch64-asm.c
@@ -126,7 +126,7 @@ aarch64_ins_reglane (const aarch64_operand *self, const aarch64_opnd_info *info,
unsigned reglane_index = info->reglane.index;
switch (info->qualifier)
{
- case AARCH64_OPND_QLF_S_B:
+ case AARCH64_OPND_QLF_S_4B:
/* L:H */
assert (reglane_index < 4);
insert_fields (code, reglane_index, 0, 2, FLD_L, FLD_H);
diff --git a/opcodes/aarch64-dis.c b/opcodes/aarch64-dis.c
index 8fd1ecf..aa38adb 100644
--- a/opcodes/aarch64-dis.c
+++ b/opcodes/aarch64-dis.c
@@ -331,7 +331,7 @@ aarch64_ext_reglane (const aarch64_operand *self, aarch64_opnd_info *info,
info->qualifier = get_expected_qualifier (inst, info->idx);
switch (info->qualifier)
{
- case AARCH64_OPND_QLF_S_B:
+ case AARCH64_OPND_QLF_S_4B:
/* L:H */
info->reglane.index = extract_fields (code, 0, 2, FLD_H, FLD_L);
info->reglane.regno &= 0x1f;
diff --git a/opcodes/aarch64-opc.c b/opcodes/aarch64-opc.c
index eac0279..2cccb0c 100644
--- a/opcodes/aarch64-opc.c
+++ b/opcodes/aarch64-opc.c
@@ -698,6 +698,7 @@ struct operand_qualifier_data aarch64_opnd_qualifiers[] =
{4, 1, 0x2, "s", OQK_OPD_VARIANT},
{8, 1, 0x3, "d", OQK_OPD_VARIANT},
{16, 1, 0x4, "q", OQK_OPD_VARIANT},
+ {1, 4, 0x0, "4b", OQK_OPD_VARIANT},
{1, 4, 0x0, "4b", OQK_OPD_VARIANT},
{1, 8, 0x0, "8b", OQK_OPD_VARIANT},
diff --git a/opcodes/aarch64-tbl.h b/opcodes/aarch64-tbl.h
index 11587dc..e38ab20 100644
--- a/opcodes/aarch64-tbl.h
+++ b/opcodes/aarch64-tbl.h
@@ -1992,8 +1992,8 @@
/* e.g. UDOT <Vd>.2S, <Vn>.8B, <Vm>.4B[<index>]. */
#define QL_V2DOT \
{ \
- QLF3(V_2S, V_8B, S_B),\
- QLF3(V_4S, V_16B, S_B),\
+ QLF3(V_2S, V_8B, S_4B),\
+ QLF3(V_4S, V_16B, S_4B),\
}
/* e.g. SHA512H <Qd>, <Qn>, <Vm>.2D . */