cpu/

* frv.cpu (r-store, r-store-dual, r-store-quad): Delete. (rstb, rsth, rst, rstd, rstq): Delete. (rstbf, rsthf, rstf, rstdf, rstqf): Delete. gas/testsuite/ * gas/frv/allinsn.s (rstb, rsth, rst, rstd, rstq): Replace with nops. (rstbf, rsthf, rstf, rstdf, rstqf): Likewise. * gas/frv/allinsn.d: Update accordingly. opcodes/ * frv-desc.c, frv-opc.c, frv-opc.h: Regenerate. sim/frv/ * decode.c, decode.h, model.c, sem.c: Regenerate. sim/testsuite/ * sim/frv/{rstb,rsth,rst,rstd,rstq}.cgs: Delete. * sim/frv/{rstbf,rsthf,rstf,rstdf,rstqf}.cgs: Delete.
author: Richard Sandiford <rdsandiford@googlemail.com> 2004-03-01 09:26:33 +0000
committer: Richard Sandiford <rdsandiford@googlemail.com> 2004-03-01 09:26:33 +0000
commit: 8ae0baa2685df96375cc43b44b5632044288f74a (patch)
tree: f66d697cb45e2fb7bb61ddd1e25047cfd75f4e65 /sim
parent: 3ce2bf1815f79e33ffbcebcf7da5f6896536f390 (diff)
download: fsf-binutils-gdb-8ae0baa2685df96375cc43b44b5632044288f74a.zip
fsf-binutils-gdb-8ae0baa2685df96375cc43b44b5632044288f74a.tar.gz
fsf-binutils-gdb-8ae0baa2685df96375cc43b44b5632044288f74a.tar.bz2
16 files changed, 151 insertions, 3172 deletions
diff --git a/sim/frv/ChangeLog b/sim/frv/ChangeLog
index 68b33ec..41462a3 100644
--- a/sim/frv/ChangeLog
+++ b/sim/frv/ChangeLog
@@ -1,3 +1,7 @@
+2004-03-01  Richard Sandiford  <rsandifo@redhat.com>
+
+	* decode.c, decode.h, model.c, sem.c: Regenerate.
+
 2003-11-24  Kevin Buettner  <kevinb@redhat.com>
 
 	* frv-sim.h (GR_REGNUM_MAX, FR_REGNUM_MAX, PC_REGNUM, SPR_REGNUM_MIN)
diff --git a/sim/frv/decode.c b/sim/frv/decode.c
index ef6be5a..cd3d6ac 100644
--- a/sim/frv/decode.c
+++ b/sim/frv/decode.c
@@ -223,22 +223,12 @@ static const struct insn_sem frvbf_insn_sem[] =
   { FRV_INSN_STHF, FRVBF_INSN_STHF, FRVBF_SFMT_STBF },
   { FRV_INSN_STF, FRVBF_INSN_STF, FRVBF_SFMT_STBF },
   { FRV_INSN_STC, FRVBF_INSN_STC, FRVBF_SFMT_STC },
-  { FRV_INSN_RSTB, FRVBF_INSN_RSTB, FRVBF_SFMT_RSTB },
-  { FRV_INSN_RSTH, FRVBF_INSN_RSTH, FRVBF_SFMT_RSTB },
-  { FRV_INSN_RST, FRVBF_INSN_RST, FRVBF_SFMT_RSTB },
-  { FRV_INSN_RSTBF, FRVBF_INSN_RSTBF, FRVBF_SFMT_RSTBF },
-  { FRV_INSN_RSTHF, FRVBF_INSN_RSTHF, FRVBF_SFMT_RSTBF },
-  { FRV_INSN_RSTF, FRVBF_INSN_RSTF, FRVBF_SFMT_RSTBF },
   { FRV_INSN_STD, FRVBF_INSN_STD, FRVBF_SFMT_STD },
   { FRV_INSN_STDF, FRVBF_INSN_STDF, FRVBF_SFMT_STDF },
   { FRV_INSN_STDC, FRVBF_INSN_STDC, FRVBF_SFMT_STDC },
-  { FRV_INSN_RSTD, FRVBF_INSN_RSTD, FRVBF_SFMT_RSTD },
-  { FRV_INSN_RSTDF, FRVBF_INSN_RSTDF, FRVBF_SFMT_RSTDF },
   { FRV_INSN_STQ, FRVBF_INSN_STQ, FRVBF_SFMT_LDQ },
   { FRV_INSN_STQF, FRVBF_INSN_STQF, FRVBF_SFMT_LDQF },
   { FRV_INSN_STQC, FRVBF_INSN_STQC, FRVBF_SFMT_LDQC },
-  { FRV_INSN_RSTQ, FRVBF_INSN_RSTQ, FRVBF_SFMT_LDQ },
-  { FRV_INSN_RSTQF, FRVBF_INSN_RSTQF, FRVBF_SFMT_LDQF },
   { FRV_INSN_STBU, FRVBF_INSN_STBU, FRVBF_SFMT_STBU },
   { FRV_INSN_STHU, FRVBF_INSN_STHU, FRVBF_SFMT_STBU },
   { FRV_INSN_STU, FRVBF_INSN_STU, FRVBF_SFMT_STBU },
@@ -1014,19 +1004,9 @@ frvbf_decode (SIM_CPU *current_cpu, IADDR pc,
           case 26 : itype = FRVBF_INSN_STFU; goto extract_sfmt_stbfu;
           case 27 : itype = FRVBF_INSN_STDFU; goto extract_sfmt_stdfu;
           case 28 : itype = FRVBF_INSN_STQFU; goto extract_sfmt_ldqfu;
-          case 32 : itype = FRVBF_INSN_RSTB; goto extract_sfmt_rstb;
-          case 33 : itype = FRVBF_INSN_RSTH; goto extract_sfmt_rstb;
-          case 34 : itype = FRVBF_INSN_RST; goto extract_sfmt_rstb;
-          case 35 : itype = FRVBF_INSN_RSTD; goto extract_sfmt_rstd;
-          case 36 : itype = FRVBF_INSN_RSTQ; goto extract_sfmt_ldq;
           case 37 : itype = FRVBF_INSN_STC; goto extract_sfmt_stc;
           case 38 : itype = FRVBF_INSN_STDC; goto extract_sfmt_stdc;
           case 39 : itype = FRVBF_INSN_STQC; goto extract_sfmt_ldqc;
-          case 40 : itype = FRVBF_INSN_RSTBF; goto extract_sfmt_rstbf;
-          case 41 : itype = FRVBF_INSN_RSTHF; goto extract_sfmt_rstbf;
-          case 42 : itype = FRVBF_INSN_RSTF; goto extract_sfmt_rstbf;
-          case 43 : itype = FRVBF_INSN_RSTDF; goto extract_sfmt_rstdf;
-          case 44 : itype = FRVBF_INSN_RSTQF; goto extract_sfmt_ldqf;
           case 45 : itype = FRVBF_INSN_STCU; goto extract_sfmt_stcu;
           case 46 : itype = FRVBF_INSN_STDCU; goto extract_sfmt_stdcu;
           case 47 : itype = FRVBF_INSN_STQCU; goto extract_sfmt_ldqcu;
@@ -4617,70 +4597,6 @@ frvbf_decode (SIM_CPU *current_cpu, IADDR pc,
     return idesc;
   }
 
- extract_sfmt_rstb:
-  {
-    const IDESC *idesc = &frvbf_insn_data[itype];
-    CGEN_INSN_INT insn = entire_insn;
-#define FLD(f) abuf->fields.sfmt_cswap.f
-    UINT f_GRk;
-    UINT f_GRi;
-    UINT f_GRj;
-
-    f_GRk = EXTRACT_LSB0_UINT (insn, 32, 30, 6);
-    f_GRi = EXTRACT_LSB0_UINT (insn, 32, 17, 6);
-    f_GRj = EXTRACT_LSB0_UINT (insn, 32, 5, 6);
-
-  /* Record the fields for the semantic handler.  */
-  FLD (f_GRi) = f_GRi;
-  FLD (f_GRj) = f_GRj;
-  FLD (f_GRk) = f_GRk;
-  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_rstb", "f_GRi 0x%x", 'x', f_GRi, "f_GRj 0x%x", 'x', f_GRj, "f_GRk 0x%x", 'x', f_GRk, (char *) 0));
-
-#if WITH_PROFILE_MODEL_P
-  /* Record the fields for profiling.  */
-  if (PROFILE_MODEL_P (current_cpu))
-    {
-      FLD (in_GRi) = f_GRi;
-      FLD (in_GRj) = f_GRj;
-      FLD (in_GRk) = f_GRk;
-    }
-#endif
-#undef FLD
-    return idesc;
-  }
-
- extract_sfmt_rstbf:
-  {
-    const IDESC *idesc = &frvbf_insn_data[itype];
-    CGEN_INSN_INT insn = entire_insn;
-#define FLD(f) abuf->fields.sfmt_cstbfu.f
-    UINT f_FRk;
-    UINT f_GRi;
-    UINT f_GRj;
-
-    f_FRk = EXTRACT_LSB0_UINT (insn, 32, 30, 6);
-    f_GRi = EXTRACT_LSB0_UINT (insn, 32, 17, 6);
-    f_GRj = EXTRACT_LSB0_UINT (insn, 32, 5, 6);
-
-  /* Record the fields for the semantic handler.  */
-  FLD (f_FRk) = f_FRk;
-  FLD (f_GRi) = f_GRi;
-  FLD (f_GRj) = f_GRj;
-  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_rstbf", "f_FRk 0x%x", 'x', f_FRk, "f_GRi 0x%x", 'x', f_GRi, "f_GRj 0x%x", 'x', f_GRj, (char *) 0));
-
-#if WITH_PROFILE_MODEL_P
-  /* Record the fields for profiling.  */
-  if (PROFILE_MODEL_P (current_cpu))
-    {
-      FLD (in_FRintk) = f_FRk;
-      FLD (in_GRi) = f_GRi;
-      FLD (in_GRj) = f_GRj;
-    }
-#endif
-#undef FLD
-    return idesc;
-  }
-
  extract_sfmt_std:
   {
     const IDESC *idesc = &frvbf_insn_data[itype];
@@ -4777,70 +4693,6 @@ frvbf_decode (SIM_CPU *current_cpu, IADDR pc,
     return idesc;
   }
 
- extract_sfmt_rstd:
-  {
-    const IDESC *idesc = &frvbf_insn_data[itype];
-    CGEN_INSN_INT insn = entire_insn;
-#define FLD(f) abuf->fields.sfmt_cstdu.f
-    UINT f_GRk;
-    UINT f_GRi;
-    UINT f_GRj;
-
-    f_GRk = EXTRACT_LSB0_UINT (insn, 32, 30, 6);
-    f_GRi = EXTRACT_LSB0_UINT (insn, 32, 17, 6);
-    f_GRj = EXTRACT_LSB0_UINT (insn, 32, 5, 6);
-
-  /* Record the fields for the semantic handler.  */
-  FLD (f_GRk) = f_GRk;
-  FLD (f_GRi) = f_GRi;
-  FLD (f_GRj) = f_GRj;
-  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_rstd", "f_GRk 0x%x", 'x', f_GRk, "f_GRi 0x%x", 'x', f_GRi, "f_GRj 0x%x", 'x', f_GRj, (char *) 0));
-
-#if WITH_PROFILE_MODEL_P
-  /* Record the fields for profiling.  */
-  if (PROFILE_MODEL_P (current_cpu))
-    {
-      FLD (in_GRdoublek) = f_GRk;
-      FLD (in_GRi) = f_GRi;
-      FLD (in_GRj) = f_GRj;
-    }
-#endif
-#undef FLD
-    return idesc;
-  }
-
- extract_sfmt_rstdf:
-  {
-    const IDESC *idesc = &frvbf_insn_data[itype];
-    CGEN_INSN_INT insn = entire_insn;
-#define FLD(f) abuf->fields.sfmt_cstdfu.f
-    UINT f_FRk;
-    UINT f_GRi;
-    UINT f_GRj;
-
-    f_FRk = EXTRACT_LSB0_UINT (insn, 32, 30, 6);
-    f_GRi = EXTRACT_LSB0_UINT (insn, 32, 17, 6);
-    f_GRj = EXTRACT_LSB0_UINT (insn, 32, 5, 6);
-
-  /* Record the fields for the semantic handler.  */
-  FLD (f_FRk) = f_FRk;
-  FLD (f_GRi) = f_GRi;
-  FLD (f_GRj) = f_GRj;
-  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_rstdf", "f_FRk 0x%x", 'x', f_FRk, "f_GRi 0x%x", 'x', f_GRi, "f_GRj 0x%x", 'x', f_GRj, (char *) 0));
-
-#if WITH_PROFILE_MODEL_P
-  /* Record the fields for profiling.  */
-  if (PROFILE_MODEL_P (current_cpu))
-    {
-      FLD (in_FRdoublek) = f_FRk;
-      FLD (in_GRi) = f_GRi;
-      FLD (in_GRj) = f_GRj;
-    }
-#endif
-#undef FLD
-    return idesc;
-  }
-
  extract_sfmt_stbu:
   {
     const IDESC *idesc = &frvbf_insn_data[itype];
diff --git a/sim/frv/decode.h b/sim/frv/decode.h
index 9741d36..386baa4 100644
--- a/sim/frv/decode.h
+++ b/sim/frv/decode.h
@@ -79,150 +79,147 @@ typedef enum frvbf_insn_type {
  , FRVBF_INSN_NLDFI, FRVBF_INSN_LDDI, FRVBF_INSN_LDDFI, FRVBF_INSN_NLDDI
  , FRVBF_INSN_NLDDFI, FRVBF_INSN_LDQI, FRVBF_INSN_LDQFI, FRVBF_INSN_NLDQFI
  , FRVBF_INSN_STB, FRVBF_INSN_STH, FRVBF_INSN_ST, FRVBF_INSN_STBF
- , FRVBF_INSN_STHF, FRVBF_INSN_STF, FRVBF_INSN_STC, FRVBF_INSN_RSTB
- , FRVBF_INSN_RSTH, FRVBF_INSN_RST, FRVBF_INSN_RSTBF, FRVBF_INSN_RSTHF
- , FRVBF_INSN_RSTF, FRVBF_INSN_STD, FRVBF_INSN_STDF, FRVBF_INSN_STDC
- , FRVBF_INSN_RSTD, FRVBF_INSN_RSTDF, FRVBF_INSN_STQ, FRVBF_INSN_STQF
- , FRVBF_INSN_STQC, FRVBF_INSN_RSTQ, FRVBF_INSN_RSTQF, FRVBF_INSN_STBU
- , FRVBF_INSN_STHU, FRVBF_INSN_STU, FRVBF_INSN_STBFU, FRVBF_INSN_STHFU
- , FRVBF_INSN_STFU, FRVBF_INSN_STCU, FRVBF_INSN_STDU, FRVBF_INSN_STDFU
- , FRVBF_INSN_STDCU, FRVBF_INSN_STQU, FRVBF_INSN_STQFU, FRVBF_INSN_STQCU
- , FRVBF_INSN_CLDSB, FRVBF_INSN_CLDUB, FRVBF_INSN_CLDSH, FRVBF_INSN_CLDUH
- , FRVBF_INSN_CLD, FRVBF_INSN_CLDBF, FRVBF_INSN_CLDHF, FRVBF_INSN_CLDF
- , FRVBF_INSN_CLDD, FRVBF_INSN_CLDDF, FRVBF_INSN_CLDQ, FRVBF_INSN_CLDSBU
- , FRVBF_INSN_CLDUBU, FRVBF_INSN_CLDSHU, FRVBF_INSN_CLDUHU, FRVBF_INSN_CLDU
- , FRVBF_INSN_CLDBFU, FRVBF_INSN_CLDHFU, FRVBF_INSN_CLDFU, FRVBF_INSN_CLDDU
- , FRVBF_INSN_CLDDFU, FRVBF_INSN_CLDQU, FRVBF_INSN_CSTB, FRVBF_INSN_CSTH
- , FRVBF_INSN_CST, FRVBF_INSN_CSTBF, FRVBF_INSN_CSTHF, FRVBF_INSN_CSTF
- , FRVBF_INSN_CSTD, FRVBF_INSN_CSTDF, FRVBF_INSN_CSTQ, FRVBF_INSN_CSTBU
- , FRVBF_INSN_CSTHU, FRVBF_INSN_CSTU, FRVBF_INSN_CSTBFU, FRVBF_INSN_CSTHFU
- , FRVBF_INSN_CSTFU, FRVBF_INSN_CSTDU, FRVBF_INSN_CSTDFU, FRVBF_INSN_STBI
- , FRVBF_INSN_STHI, FRVBF_INSN_STI, FRVBF_INSN_STBFI, FRVBF_INSN_STHFI
- , FRVBF_INSN_STFI, FRVBF_INSN_STDI, FRVBF_INSN_STDFI, FRVBF_INSN_STQI
- , FRVBF_INSN_STQFI, FRVBF_INSN_SWAP, FRVBF_INSN_SWAPI, FRVBF_INSN_CSWAP
- , FRVBF_INSN_MOVGF, FRVBF_INSN_MOVFG, FRVBF_INSN_MOVGFD, FRVBF_INSN_MOVFGD
- , FRVBF_INSN_MOVGFQ, FRVBF_INSN_MOVFGQ, FRVBF_INSN_CMOVGF, FRVBF_INSN_CMOVFG
- , FRVBF_INSN_CMOVGFD, FRVBF_INSN_CMOVFGD, FRVBF_INSN_MOVGS, FRVBF_INSN_MOVSG
- , FRVBF_INSN_BRA, FRVBF_INSN_BNO, FRVBF_INSN_BEQ, FRVBF_INSN_BNE
- , FRVBF_INSN_BLE, FRVBF_INSN_BGT, FRVBF_INSN_BLT, FRVBF_INSN_BGE
- , FRVBF_INSN_BLS, FRVBF_INSN_BHI, FRVBF_INSN_BC, FRVBF_INSN_BNC
- , FRVBF_INSN_BN, FRVBF_INSN_BP, FRVBF_INSN_BV, FRVBF_INSN_BNV
- , FRVBF_INSN_FBRA, FRVBF_INSN_FBNO, FRVBF_INSN_FBNE, FRVBF_INSN_FBEQ
- , FRVBF_INSN_FBLG, FRVBF_INSN_FBUE, FRVBF_INSN_FBUL, FRVBF_INSN_FBGE
- , FRVBF_INSN_FBLT, FRVBF_INSN_FBUGE, FRVBF_INSN_FBUG, FRVBF_INSN_FBLE
- , FRVBF_INSN_FBGT, FRVBF_INSN_FBULE, FRVBF_INSN_FBU, FRVBF_INSN_FBO
- , FRVBF_INSN_BCTRLR, FRVBF_INSN_BRALR, FRVBF_INSN_BNOLR, FRVBF_INSN_BEQLR
- , FRVBF_INSN_BNELR, FRVBF_INSN_BLELR, FRVBF_INSN_BGTLR, FRVBF_INSN_BLTLR
- , FRVBF_INSN_BGELR, FRVBF_INSN_BLSLR, FRVBF_INSN_BHILR, FRVBF_INSN_BCLR
- , FRVBF_INSN_BNCLR, FRVBF_INSN_BNLR, FRVBF_INSN_BPLR, FRVBF_INSN_BVLR
- , FRVBF_INSN_BNVLR, FRVBF_INSN_FBRALR, FRVBF_INSN_FBNOLR, FRVBF_INSN_FBEQLR
- , FRVBF_INSN_FBNELR, FRVBF_INSN_FBLGLR, FRVBF_INSN_FBUELR, FRVBF_INSN_FBULLR
- , FRVBF_INSN_FBGELR, FRVBF_INSN_FBLTLR, FRVBF_INSN_FBUGELR, FRVBF_INSN_FBUGLR
- , FRVBF_INSN_FBLELR, FRVBF_INSN_FBGTLR, FRVBF_INSN_FBULELR, FRVBF_INSN_FBULR
- , FRVBF_INSN_FBOLR, FRVBF_INSN_BCRALR, FRVBF_INSN_BCNOLR, FRVBF_INSN_BCEQLR
- , FRVBF_INSN_BCNELR, FRVBF_INSN_BCLELR, FRVBF_INSN_BCGTLR, FRVBF_INSN_BCLTLR
- , FRVBF_INSN_BCGELR, FRVBF_INSN_BCLSLR, FRVBF_INSN_BCHILR, FRVBF_INSN_BCCLR
- , FRVBF_INSN_BCNCLR, FRVBF_INSN_BCNLR, FRVBF_INSN_BCPLR, FRVBF_INSN_BCVLR
- , FRVBF_INSN_BCNVLR, FRVBF_INSN_FCBRALR, FRVBF_INSN_FCBNOLR, FRVBF_INSN_FCBEQLR
- , FRVBF_INSN_FCBNELR, FRVBF_INSN_FCBLGLR, FRVBF_INSN_FCBUELR, FRVBF_INSN_FCBULLR
- , FRVBF_INSN_FCBGELR, FRVBF_INSN_FCBLTLR, FRVBF_INSN_FCBUGELR, FRVBF_INSN_FCBUGLR
- , FRVBF_INSN_FCBLELR, FRVBF_INSN_FCBGTLR, FRVBF_INSN_FCBULELR, FRVBF_INSN_FCBULR
- , FRVBF_INSN_FCBOLR, FRVBF_INSN_JMPL, FRVBF_INSN_CALLL, FRVBF_INSN_JMPIL
- , FRVBF_INSN_CALLIL, FRVBF_INSN_CALL, FRVBF_INSN_RETT, FRVBF_INSN_REI
- , FRVBF_INSN_TRA, FRVBF_INSN_TNO, FRVBF_INSN_TEQ, FRVBF_INSN_TNE
- , FRVBF_INSN_TLE, FRVBF_INSN_TGT, FRVBF_INSN_TLT, FRVBF_INSN_TGE
- , FRVBF_INSN_TLS, FRVBF_INSN_THI, FRVBF_INSN_TC, FRVBF_INSN_TNC
- , FRVBF_INSN_TN, FRVBF_INSN_TP, FRVBF_INSN_TV, FRVBF_INSN_TNV
- , FRVBF_INSN_FTRA, FRVBF_INSN_FTNO, FRVBF_INSN_FTNE, FRVBF_INSN_FTEQ
- , FRVBF_INSN_FTLG, FRVBF_INSN_FTUE, FRVBF_INSN_FTUL, FRVBF_INSN_FTGE
- , FRVBF_INSN_FTLT, FRVBF_INSN_FTUGE, FRVBF_INSN_FTUG, FRVBF_INSN_FTLE
- , FRVBF_INSN_FTGT, FRVBF_INSN_FTULE, FRVBF_INSN_FTU, FRVBF_INSN_FTO
- , FRVBF_INSN_TIRA, FRVBF_INSN_TINO, FRVBF_INSN_TIEQ, FRVBF_INSN_TINE
- , FRVBF_INSN_TILE, FRVBF_INSN_TIGT, FRVBF_INSN_TILT, FRVBF_INSN_TIGE
- , FRVBF_INSN_TILS, FRVBF_INSN_TIHI, FRVBF_INSN_TIC, FRVBF_INSN_TINC
- , FRVBF_INSN_TIN, FRVBF_INSN_TIP, FRVBF_INSN_TIV, FRVBF_INSN_TINV
- , FRVBF_INSN_FTIRA, FRVBF_INSN_FTINO, FRVBF_INSN_FTINE, FRVBF_INSN_FTIEQ
- , FRVBF_INSN_FTILG, FRVBF_INSN_FTIUE, FRVBF_INSN_FTIUL, FRVBF_INSN_FTIGE
- , FRVBF_INSN_FTILT, FRVBF_INSN_FTIUGE, FRVBF_INSN_FTIUG, FRVBF_INSN_FTILE
- , FRVBF_INSN_FTIGT, FRVBF_INSN_FTIULE, FRVBF_INSN_FTIU, FRVBF_INSN_FTIO
- , FRVBF_INSN_BREAK, FRVBF_INSN_MTRAP, FRVBF_INSN_ANDCR, FRVBF_INSN_ORCR
- , FRVBF_INSN_XORCR, FRVBF_INSN_NANDCR, FRVBF_INSN_NORCR, FRVBF_INSN_ANDNCR
- , FRVBF_INSN_ORNCR, FRVBF_INSN_NANDNCR, FRVBF_INSN_NORNCR, FRVBF_INSN_NOTCR
- , FRVBF_INSN_CKRA, FRVBF_INSN_CKNO, FRVBF_INSN_CKEQ, FRVBF_INSN_CKNE
- , FRVBF_INSN_CKLE, FRVBF_INSN_CKGT, FRVBF_INSN_CKLT, FRVBF_INSN_CKGE
- , FRVBF_INSN_CKLS, FRVBF_INSN_CKHI, FRVBF_INSN_CKC, FRVBF_INSN_CKNC
- , FRVBF_INSN_CKN, FRVBF_INSN_CKP, FRVBF_INSN_CKV, FRVBF_INSN_CKNV
- , FRVBF_INSN_FCKRA, FRVBF_INSN_FCKNO, FRVBF_INSN_FCKNE, FRVBF_INSN_FCKEQ
- , FRVBF_INSN_FCKLG, FRVBF_INSN_FCKUE, FRVBF_INSN_FCKUL, FRVBF_INSN_FCKGE
- , FRVBF_INSN_FCKLT, FRVBF_INSN_FCKUGE, FRVBF_INSN_FCKUG, FRVBF_INSN_FCKLE
- , FRVBF_INSN_FCKGT, FRVBF_INSN_FCKULE, FRVBF_INSN_FCKU, FRVBF_INSN_FCKO
- , FRVBF_INSN_CCKRA, FRVBF_INSN_CCKNO, FRVBF_INSN_CCKEQ, FRVBF_INSN_CCKNE
- , FRVBF_INSN_CCKLE, FRVBF_INSN_CCKGT, FRVBF_INSN_CCKLT, FRVBF_INSN_CCKGE
- , FRVBF_INSN_CCKLS, FRVBF_INSN_CCKHI, FRVBF_INSN_CCKC, FRVBF_INSN_CCKNC
- , FRVBF_INSN_CCKN, FRVBF_INSN_CCKP, FRVBF_INSN_CCKV, FRVBF_INSN_CCKNV
- , FRVBF_INSN_CFCKRA, FRVBF_INSN_CFCKNO, FRVBF_INSN_CFCKNE, FRVBF_INSN_CFCKEQ
- , FRVBF_INSN_CFCKLG, FRVBF_INSN_CFCKUE, FRVBF_INSN_CFCKUL, FRVBF_INSN_CFCKGE
- , FRVBF_INSN_CFCKLT, FRVBF_INSN_CFCKUGE, FRVBF_INSN_CFCKUG, FRVBF_INSN_CFCKLE
- , FRVBF_INSN_CFCKGT, FRVBF_INSN_CFCKULE, FRVBF_INSN_CFCKU, FRVBF_INSN_CFCKO
- , FRVBF_INSN_CJMPL, FRVBF_INSN_CCALLL, FRVBF_INSN_ICI, FRVBF_INSN_DCI
- , FRVBF_INSN_ICEI, FRVBF_INSN_DCEI, FRVBF_INSN_DCF, FRVBF_INSN_DCEF
- , FRVBF_INSN_WITLB, FRVBF_INSN_WDTLB, FRVBF_INSN_ITLBI, FRVBF_INSN_DTLBI
- , FRVBF_INSN_ICPL, FRVBF_INSN_DCPL, FRVBF_INSN_ICUL, FRVBF_INSN_DCUL
- , FRVBF_INSN_BAR, FRVBF_INSN_MEMBAR, FRVBF_INSN_COP1, FRVBF_INSN_COP2
- , FRVBF_INSN_CLRGR, FRVBF_INSN_CLRFR, FRVBF_INSN_CLRGA, FRVBF_INSN_CLRFA
- , FRVBF_INSN_COMMITGR, FRVBF_INSN_COMMITFR, FRVBF_INSN_COMMITGA, FRVBF_INSN_COMMITFA
- , FRVBF_INSN_FITOS, FRVBF_INSN_FSTOI, FRVBF_INSN_FITOD, FRVBF_INSN_FDTOI
- , FRVBF_INSN_FDITOS, FRVBF_INSN_FDSTOI, FRVBF_INSN_NFDITOS, FRVBF_INSN_NFDSTOI
- , FRVBF_INSN_CFITOS, FRVBF_INSN_CFSTOI, FRVBF_INSN_NFITOS, FRVBF_INSN_NFSTOI
- , FRVBF_INSN_FMOVS, FRVBF_INSN_FMOVD, FRVBF_INSN_FDMOVS, FRVBF_INSN_CFMOVS
- , FRVBF_INSN_FNEGS, FRVBF_INSN_FNEGD, FRVBF_INSN_FDNEGS, FRVBF_INSN_CFNEGS
- , FRVBF_INSN_FABSS, FRVBF_INSN_FABSD, FRVBF_INSN_FDABSS, FRVBF_INSN_CFABSS
- , FRVBF_INSN_FSQRTS, FRVBF_INSN_FDSQRTS, FRVBF_INSN_NFDSQRTS, FRVBF_INSN_FSQRTD
- , FRVBF_INSN_CFSQRTS, FRVBF_INSN_NFSQRTS, FRVBF_INSN_FADDS, FRVBF_INSN_FSUBS
- , FRVBF_INSN_FMULS, FRVBF_INSN_FDIVS, FRVBF_INSN_FADDD, FRVBF_INSN_FSUBD
- , FRVBF_INSN_FMULD, FRVBF_INSN_FDIVD, FRVBF_INSN_CFADDS, FRVBF_INSN_CFSUBS
- , FRVBF_INSN_CFMULS, FRVBF_INSN_CFDIVS, FRVBF_INSN_NFADDS, FRVBF_INSN_NFSUBS
- , FRVBF_INSN_NFMULS, FRVBF_INSN_NFDIVS, FRVBF_INSN_FCMPS, FRVBF_INSN_FCMPD
- , FRVBF_INSN_CFCMPS, FRVBF_INSN_FDCMPS, FRVBF_INSN_FMADDS, FRVBF_INSN_FMSUBS
- , FRVBF_INSN_FMADDD, FRVBF_INSN_FMSUBD, FRVBF_INSN_FDMADDS, FRVBF_INSN_NFDMADDS
- , FRVBF_INSN_CFMADDS, FRVBF_INSN_CFMSUBS, FRVBF_INSN_NFMADDS, FRVBF_INSN_NFMSUBS
- , FRVBF_INSN_FMAS, FRVBF_INSN_FMSS, FRVBF_INSN_FDMAS, FRVBF_INSN_FDMSS
- , FRVBF_INSN_NFDMAS, FRVBF_INSN_NFDMSS, FRVBF_INSN_CFMAS, FRVBF_INSN_CFMSS
- , FRVBF_INSN_FMAD, FRVBF_INSN_FMSD, FRVBF_INSN_NFMAS, FRVBF_INSN_NFMSS
- , FRVBF_INSN_FDADDS, FRVBF_INSN_FDSUBS, FRVBF_INSN_FDMULS, FRVBF_INSN_FDDIVS
- , FRVBF_INSN_FDSADS, FRVBF_INSN_FDMULCS, FRVBF_INSN_NFDMULCS, FRVBF_INSN_NFDADDS
- , FRVBF_INSN_NFDSUBS, FRVBF_INSN_NFDMULS, FRVBF_INSN_NFDDIVS, FRVBF_INSN_NFDSADS
- , FRVBF_INSN_NFDCMPS, FRVBF_INSN_MHSETLOS, FRVBF_INSN_MHSETHIS, FRVBF_INSN_MHDSETS
- , FRVBF_INSN_MHSETLOH, FRVBF_INSN_MHSETHIH, FRVBF_INSN_MHDSETH, FRVBF_INSN_MAND
- , FRVBF_INSN_MOR, FRVBF_INSN_MXOR, FRVBF_INSN_CMAND, FRVBF_INSN_CMOR
- , FRVBF_INSN_CMXOR, FRVBF_INSN_MNOT, FRVBF_INSN_CMNOT, FRVBF_INSN_MROTLI
- , FRVBF_INSN_MROTRI, FRVBF_INSN_MWCUT, FRVBF_INSN_MWCUTI, FRVBF_INSN_MCUT
- , FRVBF_INSN_MCUTI, FRVBF_INSN_MCUTSS, FRVBF_INSN_MCUTSSI, FRVBF_INSN_MDCUTSSI
- , FRVBF_INSN_MAVEH, FRVBF_INSN_MSLLHI, FRVBF_INSN_MSRLHI, FRVBF_INSN_MSRAHI
- , FRVBF_INSN_MDROTLI, FRVBF_INSN_MCPLHI, FRVBF_INSN_MCPLI, FRVBF_INSN_MSATHS
- , FRVBF_INSN_MQSATHS, FRVBF_INSN_MSATHU, FRVBF_INSN_MCMPSH, FRVBF_INSN_MCMPUH
- , FRVBF_INSN_MABSHS, FRVBF_INSN_MADDHSS, FRVBF_INSN_MADDHUS, FRVBF_INSN_MSUBHSS
- , FRVBF_INSN_MSUBHUS, FRVBF_INSN_CMADDHSS, FRVBF_INSN_CMADDHUS, FRVBF_INSN_CMSUBHSS
- , FRVBF_INSN_CMSUBHUS, FRVBF_INSN_MQADDHSS, FRVBF_INSN_MQADDHUS, FRVBF_INSN_MQSUBHSS
- , FRVBF_INSN_MQSUBHUS, FRVBF_INSN_CMQADDHSS, FRVBF_INSN_CMQADDHUS, FRVBF_INSN_CMQSUBHSS
- , FRVBF_INSN_CMQSUBHUS, FRVBF_INSN_MADDACCS, FRVBF_INSN_MSUBACCS, FRVBF_INSN_MDADDACCS
- , FRVBF_INSN_MDSUBACCS, FRVBF_INSN_MASACCS, FRVBF_INSN_MDASACCS, FRVBF_INSN_MMULHS
- , FRVBF_INSN_MMULHU, FRVBF_INSN_MMULXHS, FRVBF_INSN_MMULXHU, FRVBF_INSN_CMMULHS
- , FRVBF_INSN_CMMULHU, FRVBF_INSN_MQMULHS, FRVBF_INSN_MQMULHU, FRVBF_INSN_MQMULXHS
- , FRVBF_INSN_MQMULXHU, FRVBF_INSN_CMQMULHS, FRVBF_INSN_CMQMULHU, FRVBF_INSN_MMACHS
- , FRVBF_INSN_MMACHU, FRVBF_INSN_MMRDHS, FRVBF_INSN_MMRDHU, FRVBF_INSN_CMMACHS
- , FRVBF_INSN_CMMACHU, FRVBF_INSN_MQMACHS, FRVBF_INSN_MQMACHU, FRVBF_INSN_CMQMACHS
- , FRVBF_INSN_CMQMACHU, FRVBF_INSN_MQXMACHS, FRVBF_INSN_MQXMACXHS, FRVBF_INSN_MQMACXHS
- , FRVBF_INSN_MCPXRS, FRVBF_INSN_MCPXRU, FRVBF_INSN_MCPXIS, FRVBF_INSN_MCPXIU
- , FRVBF_INSN_CMCPXRS, FRVBF_INSN_CMCPXRU, FRVBF_INSN_CMCPXIS, FRVBF_INSN_CMCPXIU
- , FRVBF_INSN_MQCPXRS, FRVBF_INSN_MQCPXRU, FRVBF_INSN_MQCPXIS, FRVBF_INSN_MQCPXIU
- , FRVBF_INSN_MEXPDHW, FRVBF_INSN_CMEXPDHW, FRVBF_INSN_MEXPDHD, FRVBF_INSN_CMEXPDHD
- , FRVBF_INSN_MPACKH, FRVBF_INSN_MDPACKH, FRVBF_INSN_MUNPACKH, FRVBF_INSN_MDUNPACKH
- , FRVBF_INSN_MBTOH, FRVBF_INSN_CMBTOH, FRVBF_INSN_MHTOB, FRVBF_INSN_CMHTOB
- , FRVBF_INSN_MBTOHE, FRVBF_INSN_CMBTOHE, FRVBF_INSN_MNOP, FRVBF_INSN_MCLRACC_0
- , FRVBF_INSN_MCLRACC_1, FRVBF_INSN_MRDACC, FRVBF_INSN_MRDACCG, FRVBF_INSN_MWTACC
- , FRVBF_INSN_MWTACCG, FRVBF_INSN_MCOP1, FRVBF_INSN_MCOP2, FRVBF_INSN_FNOP
- , FRVBF_INSN__MAX
+ , FRVBF_INSN_STHF, FRVBF_INSN_STF, FRVBF_INSN_STC, FRVBF_INSN_STD
+ , FRVBF_INSN_STDF, FRVBF_INSN_STDC, FRVBF_INSN_STQ, FRVBF_INSN_STQF
+ , FRVBF_INSN_STQC, FRVBF_INSN_STBU, FRVBF_INSN_STHU, FRVBF_INSN_STU
+ , FRVBF_INSN_STBFU, FRVBF_INSN_STHFU, FRVBF_INSN_STFU, FRVBF_INSN_STCU
+ , FRVBF_INSN_STDU, FRVBF_INSN_STDFU, FRVBF_INSN_STDCU, FRVBF_INSN_STQU
+ , FRVBF_INSN_STQFU, FRVBF_INSN_STQCU, FRVBF_INSN_CLDSB, FRVBF_INSN_CLDUB
+ , FRVBF_INSN_CLDSH, FRVBF_INSN_CLDUH, FRVBF_INSN_CLD, FRVBF_INSN_CLDBF
+ , FRVBF_INSN_CLDHF, FRVBF_INSN_CLDF, FRVBF_INSN_CLDD, FRVBF_INSN_CLDDF
+ , FRVBF_INSN_CLDQ, FRVBF_INSN_CLDSBU, FRVBF_INSN_CLDUBU, FRVBF_INSN_CLDSHU
+ , FRVBF_INSN_CLDUHU, FRVBF_INSN_CLDU, FRVBF_INSN_CLDBFU, FRVBF_INSN_CLDHFU
+ , FRVBF_INSN_CLDFU, FRVBF_INSN_CLDDU, FRVBF_INSN_CLDDFU, FRVBF_INSN_CLDQU
+ , FRVBF_INSN_CSTB, FRVBF_INSN_CSTH, FRVBF_INSN_CST, FRVBF_INSN_CSTBF
+ , FRVBF_INSN_CSTHF, FRVBF_INSN_CSTF, FRVBF_INSN_CSTD, FRVBF_INSN_CSTDF
+ , FRVBF_INSN_CSTQ, FRVBF_INSN_CSTBU, FRVBF_INSN_CSTHU, FRVBF_INSN_CSTU
+ , FRVBF_INSN_CSTBFU, FRVBF_INSN_CSTHFU, FRVBF_INSN_CSTFU, FRVBF_INSN_CSTDU
+ , FRVBF_INSN_CSTDFU, FRVBF_INSN_STBI, FRVBF_INSN_STHI, FRVBF_INSN_STI
+ , FRVBF_INSN_STBFI, FRVBF_INSN_STHFI, FRVBF_INSN_STFI, FRVBF_INSN_STDI
+ , FRVBF_INSN_STDFI, FRVBF_INSN_STQI, FRVBF_INSN_STQFI, FRVBF_INSN_SWAP
+ , FRVBF_INSN_SWAPI, FRVBF_INSN_CSWAP, FRVBF_INSN_MOVGF, FRVBF_INSN_MOVFG
+ , FRVBF_INSN_MOVGFD, FRVBF_INSN_MOVFGD, FRVBF_INSN_MOVGFQ, FRVBF_INSN_MOVFGQ
+ , FRVBF_INSN_CMOVGF, FRVBF_INSN_CMOVFG, FRVBF_INSN_CMOVGFD, FRVBF_INSN_CMOVFGD
+ , FRVBF_INSN_MOVGS, FRVBF_INSN_MOVSG, FRVBF_INSN_BRA, FRVBF_INSN_BNO
+ , FRVBF_INSN_BEQ, FRVBF_INSN_BNE, FRVBF_INSN_BLE, FRVBF_INSN_BGT
+ , FRVBF_INSN_BLT, FRVBF_INSN_BGE, FRVBF_INSN_BLS, FRVBF_INSN_BHI
+ , FRVBF_INSN_BC, FRVBF_INSN_BNC, FRVBF_INSN_BN, FRVBF_INSN_BP
+ , FRVBF_INSN_BV, FRVBF_INSN_BNV, FRVBF_INSN_FBRA, FRVBF_INSN_FBNO
+ , FRVBF_INSN_FBNE, FRVBF_INSN_FBEQ, FRVBF_INSN_FBLG, FRVBF_INSN_FBUE
+ , FRVBF_INSN_FBUL, FRVBF_INSN_FBGE, FRVBF_INSN_FBLT, FRVBF_INSN_FBUGE
+ , FRVBF_INSN_FBUG, FRVBF_INSN_FBLE, FRVBF_INSN_FBGT, FRVBF_INSN_FBULE
+ , FRVBF_INSN_FBU, FRVBF_INSN_FBO, FRVBF_INSN_BCTRLR, FRVBF_INSN_BRALR
+ , FRVBF_INSN_BNOLR, FRVBF_INSN_BEQLR, FRVBF_INSN_BNELR, FRVBF_INSN_BLELR
+ , FRVBF_INSN_BGTLR, FRVBF_INSN_BLTLR, FRVBF_INSN_BGELR, FRVBF_INSN_BLSLR
+ , FRVBF_INSN_BHILR, FRVBF_INSN_BCLR, FRVBF_INSN_BNCLR, FRVBF_INSN_BNLR
+ , FRVBF_INSN_BPLR, FRVBF_INSN_BVLR, FRVBF_INSN_BNVLR, FRVBF_INSN_FBRALR
+ , FRVBF_INSN_FBNOLR, FRVBF_INSN_FBEQLR, FRVBF_INSN_FBNELR, FRVBF_INSN_FBLGLR
+ , FRVBF_INSN_FBUELR, FRVBF_INSN_FBULLR, FRVBF_INSN_FBGELR, FRVBF_INSN_FBLTLR
+ , FRVBF_INSN_FBUGELR, FRVBF_INSN_FBUGLR, FRVBF_INSN_FBLELR, FRVBF_INSN_FBGTLR
+ , FRVBF_INSN_FBULELR, FRVBF_INSN_FBULR, FRVBF_INSN_FBOLR, FRVBF_INSN_BCRALR
+ , FRVBF_INSN_BCNOLR, FRVBF_INSN_BCEQLR, FRVBF_INSN_BCNELR, FRVBF_INSN_BCLELR
+ , FRVBF_INSN_BCGTLR, FRVBF_INSN_BCLTLR, FRVBF_INSN_BCGELR, FRVBF_INSN_BCLSLR
+ , FRVBF_INSN_BCHILR, FRVBF_INSN_BCCLR, FRVBF_INSN_BCNCLR, FRVBF_INSN_BCNLR
+ , FRVBF_INSN_BCPLR, FRVBF_INSN_BCVLR, FRVBF_INSN_BCNVLR, FRVBF_INSN_FCBRALR
+ , FRVBF_INSN_FCBNOLR, FRVBF_INSN_FCBEQLR, FRVBF_INSN_FCBNELR, FRVBF_INSN_FCBLGLR
+ , FRVBF_INSN_FCBUELR, FRVBF_INSN_FCBULLR, FRVBF_INSN_FCBGELR, FRVBF_INSN_FCBLTLR
+ , FRVBF_INSN_FCBUGELR, FRVBF_INSN_FCBUGLR, FRVBF_INSN_FCBLELR, FRVBF_INSN_FCBGTLR
+ , FRVBF_INSN_FCBULELR, FRVBF_INSN_FCBULR, FRVBF_INSN_FCBOLR, FRVBF_INSN_JMPL
+ , FRVBF_INSN_CALLL, FRVBF_INSN_JMPIL, FRVBF_INSN_CALLIL, FRVBF_INSN_CALL
+ , FRVBF_INSN_RETT, FRVBF_INSN_REI, FRVBF_INSN_TRA, FRVBF_INSN_TNO
+ , FRVBF_INSN_TEQ, FRVBF_INSN_TNE, FRVBF_INSN_TLE, FRVBF_INSN_TGT
+ , FRVBF_INSN_TLT, FRVBF_INSN_TGE, FRVBF_INSN_TLS, FRVBF_INSN_THI
+ , FRVBF_INSN_TC, FRVBF_INSN_TNC, FRVBF_INSN_TN, FRVBF_INSN_TP
+ , FRVBF_INSN_TV, FRVBF_INSN_TNV, FRVBF_INSN_FTRA, FRVBF_INSN_FTNO
+ , FRVBF_INSN_FTNE, FRVBF_INSN_FTEQ, FRVBF_INSN_FTLG, FRVBF_INSN_FTUE
+ , FRVBF_INSN_FTUL, FRVBF_INSN_FTGE, FRVBF_INSN_FTLT, FRVBF_INSN_FTUGE
+ , FRVBF_INSN_FTUG, FRVBF_INSN_FTLE, FRVBF_INSN_FTGT, FRVBF_INSN_FTULE
+ , FRVBF_INSN_FTU, FRVBF_INSN_FTO, FRVBF_INSN_TIRA, FRVBF_INSN_TINO
+ , FRVBF_INSN_TIEQ, FRVBF_INSN_TINE, FRVBF_INSN_TILE, FRVBF_INSN_TIGT
+ , FRVBF_INSN_TILT, FRVBF_INSN_TIGE, FRVBF_INSN_TILS, FRVBF_INSN_TIHI
+ , FRVBF_INSN_TIC, FRVBF_INSN_TINC, FRVBF_INSN_TIN, FRVBF_INSN_TIP
+ , FRVBF_INSN_TIV, FRVBF_INSN_TINV, FRVBF_INSN_FTIRA, FRVBF_INSN_FTINO
+ , FRVBF_INSN_FTINE, FRVBF_INSN_FTIEQ, FRVBF_INSN_FTILG, FRVBF_INSN_FTIUE
+ , FRVBF_INSN_FTIUL, FRVBF_INSN_FTIGE, FRVBF_INSN_FTILT, FRVBF_INSN_FTIUGE
+ , FRVBF_INSN_FTIUG, FRVBF_INSN_FTILE, FRVBF_INSN_FTIGT, FRVBF_INSN_FTIULE
+ , FRVBF_INSN_FTIU, FRVBF_INSN_FTIO, FRVBF_INSN_BREAK, FRVBF_INSN_MTRAP
+ , FRVBF_INSN_ANDCR, FRVBF_INSN_ORCR, FRVBF_INSN_XORCR, FRVBF_INSN_NANDCR
+ , FRVBF_INSN_NORCR, FRVBF_INSN_ANDNCR, FRVBF_INSN_ORNCR, FRVBF_INSN_NANDNCR
+ , FRVBF_INSN_NORNCR, FRVBF_INSN_NOTCR, FRVBF_INSN_CKRA, FRVBF_INSN_CKNO
+ , FRVBF_INSN_CKEQ, FRVBF_INSN_CKNE, FRVBF_INSN_CKLE, FRVBF_INSN_CKGT
+ , FRVBF_INSN_CKLT, FRVBF_INSN_CKGE, FRVBF_INSN_CKLS, FRVBF_INSN_CKHI
+ , FRVBF_INSN_CKC, FRVBF_INSN_CKNC, FRVBF_INSN_CKN, FRVBF_INSN_CKP
+ , FRVBF_INSN_CKV, FRVBF_INSN_CKNV, FRVBF_INSN_FCKRA, FRVBF_INSN_FCKNO
+ , FRVBF_INSN_FCKNE, FRVBF_INSN_FCKEQ, FRVBF_INSN_FCKLG, FRVBF_INSN_FCKUE
+ , FRVBF_INSN_FCKUL, FRVBF_INSN_FCKGE, FRVBF_INSN_FCKLT, FRVBF_INSN_FCKUGE
+ , FRVBF_INSN_FCKUG, FRVBF_INSN_FCKLE, FRVBF_INSN_FCKGT, FRVBF_INSN_FCKULE
+ , FRVBF_INSN_FCKU, FRVBF_INSN_FCKO, FRVBF_INSN_CCKRA, FRVBF_INSN_CCKNO
+ , FRVBF_INSN_CCKEQ, FRVBF_INSN_CCKNE, FRVBF_INSN_CCKLE, FRVBF_INSN_CCKGT
+ , FRVBF_INSN_CCKLT, FRVBF_INSN_CCKGE, FRVBF_INSN_CCKLS, FRVBF_INSN_CCKHI
+ , FRVBF_INSN_CCKC, FRVBF_INSN_CCKNC, FRVBF_INSN_CCKN, FRVBF_INSN_CCKP
+ , FRVBF_INSN_CCKV, FRVBF_INSN_CCKNV, FRVBF_INSN_CFCKRA, FRVBF_INSN_CFCKNO
+ , FRVBF_INSN_CFCKNE, FRVBF_INSN_CFCKEQ, FRVBF_INSN_CFCKLG, FRVBF_INSN_CFCKUE
+ , FRVBF_INSN_CFCKUL, FRVBF_INSN_CFCKGE, FRVBF_INSN_CFCKLT, FRVBF_INSN_CFCKUGE
+ , FRVBF_INSN_CFCKUG, FRVBF_INSN_CFCKLE, FRVBF_INSN_CFCKGT, FRVBF_INSN_CFCKULE
+ , FRVBF_INSN_CFCKU, FRVBF_INSN_CFCKO, FRVBF_INSN_CJMPL, FRVBF_INSN_CCALLL
+ , FRVBF_INSN_ICI, FRVBF_INSN_DCI, FRVBF_INSN_ICEI, FRVBF_INSN_DCEI
+ , FRVBF_INSN_DCF, FRVBF_INSN_DCEF, FRVBF_INSN_WITLB, FRVBF_INSN_WDTLB
+ , FRVBF_INSN_ITLBI, FRVBF_INSN_DTLBI, FRVBF_INSN_ICPL, FRVBF_INSN_DCPL
+ , FRVBF_INSN_ICUL, FRVBF_INSN_DCUL, FRVBF_INSN_BAR, FRVBF_INSN_MEMBAR
+ , FRVBF_INSN_COP1, FRVBF_INSN_COP2, FRVBF_INSN_CLRGR, FRVBF_INSN_CLRFR
+ , FRVBF_INSN_CLRGA, FRVBF_INSN_CLRFA, FRVBF_INSN_COMMITGR, FRVBF_INSN_COMMITFR
+ , FRVBF_INSN_COMMITGA, FRVBF_INSN_COMMITFA, FRVBF_INSN_FITOS, FRVBF_INSN_FSTOI
+ , FRVBF_INSN_FITOD, FRVBF_INSN_FDTOI, FRVBF_INSN_FDITOS, FRVBF_INSN_FDSTOI
+ , FRVBF_INSN_NFDITOS, FRVBF_INSN_NFDSTOI, FRVBF_INSN_CFITOS, FRVBF_INSN_CFSTOI
+ , FRVBF_INSN_NFITOS, FRVBF_INSN_NFSTOI, FRVBF_INSN_FMOVS, FRVBF_INSN_FMOVD
+ , FRVBF_INSN_FDMOVS, FRVBF_INSN_CFMOVS, FRVBF_INSN_FNEGS, FRVBF_INSN_FNEGD
+ , FRVBF_INSN_FDNEGS, FRVBF_INSN_CFNEGS, FRVBF_INSN_FABSS, FRVBF_INSN_FABSD
+ , FRVBF_INSN_FDABSS, FRVBF_INSN_CFABSS, FRVBF_INSN_FSQRTS, FRVBF_INSN_FDSQRTS
+ , FRVBF_INSN_NFDSQRTS, FRVBF_INSN_FSQRTD, FRVBF_INSN_CFSQRTS, FRVBF_INSN_NFSQRTS
+ , FRVBF_INSN_FADDS, FRVBF_INSN_FSUBS, FRVBF_INSN_FMULS, FRVBF_INSN_FDIVS
+ , FRVBF_INSN_FADDD, FRVBF_INSN_FSUBD, FRVBF_INSN_FMULD, FRVBF_INSN_FDIVD
+ , FRVBF_INSN_CFADDS, FRVBF_INSN_CFSUBS, FRVBF_INSN_CFMULS, FRVBF_INSN_CFDIVS
+ , FRVBF_INSN_NFADDS, FRVBF_INSN_NFSUBS, FRVBF_INSN_NFMULS, FRVBF_INSN_NFDIVS
+ , FRVBF_INSN_FCMPS, FRVBF_INSN_FCMPD, FRVBF_INSN_CFCMPS, FRVBF_INSN_FDCMPS
+ , FRVBF_INSN_FMADDS, FRVBF_INSN_FMSUBS, FRVBF_INSN_FMADDD, FRVBF_INSN_FMSUBD
+ , FRVBF_INSN_FDMADDS, FRVBF_INSN_NFDMADDS, FRVBF_INSN_CFMADDS, FRVBF_INSN_CFMSUBS
+ , FRVBF_INSN_NFMADDS, FRVBF_INSN_NFMSUBS, FRVBF_INSN_FMAS, FRVBF_INSN_FMSS
+ , FRVBF_INSN_FDMAS, FRVBF_INSN_FDMSS, FRVBF_INSN_NFDMAS, FRVBF_INSN_NFDMSS
+ , FRVBF_INSN_CFMAS, FRVBF_INSN_CFMSS, FRVBF_INSN_FMAD, FRVBF_INSN_FMSD
+ , FRVBF_INSN_NFMAS, FRVBF_INSN_NFMSS, FRVBF_INSN_FDADDS, FRVBF_INSN_FDSUBS
+ , FRVBF_INSN_FDMULS, FRVBF_INSN_FDDIVS, FRVBF_INSN_FDSADS, FRVBF_INSN_FDMULCS
+ , FRVBF_INSN_NFDMULCS, FRVBF_INSN_NFDADDS, FRVBF_INSN_NFDSUBS, FRVBF_INSN_NFDMULS
+ , FRVBF_INSN_NFDDIVS, FRVBF_INSN_NFDSADS, FRVBF_INSN_NFDCMPS, FRVBF_INSN_MHSETLOS
+ , FRVBF_INSN_MHSETHIS, FRVBF_INSN_MHDSETS, FRVBF_INSN_MHSETLOH, FRVBF_INSN_MHSETHIH
+ , FRVBF_INSN_MHDSETH, FRVBF_INSN_MAND, FRVBF_INSN_MOR, FRVBF_INSN_MXOR
+ , FRVBF_INSN_CMAND, FRVBF_INSN_CMOR, FRVBF_INSN_CMXOR, FRVBF_INSN_MNOT
+ , FRVBF_INSN_CMNOT, FRVBF_INSN_MROTLI, FRVBF_INSN_MROTRI, FRVBF_INSN_MWCUT
+ , FRVBF_INSN_MWCUTI, FRVBF_INSN_MCUT, FRVBF_INSN_MCUTI, FRVBF_INSN_MCUTSS
+ , FRVBF_INSN_MCUTSSI, FRVBF_INSN_MDCUTSSI, FRVBF_INSN_MAVEH, FRVBF_INSN_MSLLHI
+ , FRVBF_INSN_MSRLHI, FRVBF_INSN_MSRAHI, FRVBF_INSN_MDROTLI, FRVBF_INSN_MCPLHI
+ , FRVBF_INSN_MCPLI, FRVBF_INSN_MSATHS, FRVBF_INSN_MQSATHS, FRVBF_INSN_MSATHU
+ , FRVBF_INSN_MCMPSH, FRVBF_INSN_MCMPUH, FRVBF_INSN_MABSHS, FRVBF_INSN_MADDHSS
+ , FRVBF_INSN_MADDHUS, FRVBF_INSN_MSUBHSS, FRVBF_INSN_MSUBHUS, FRVBF_INSN_CMADDHSS
+ , FRVBF_INSN_CMADDHUS, FRVBF_INSN_CMSUBHSS, FRVBF_INSN_CMSUBHUS, FRVBF_INSN_MQADDHSS
+ , FRVBF_INSN_MQADDHUS, FRVBF_INSN_MQSUBHSS, FRVBF_INSN_MQSUBHUS, FRVBF_INSN_CMQADDHSS
+ , FRVBF_INSN_CMQADDHUS, FRVBF_INSN_CMQSUBHSS, FRVBF_INSN_CMQSUBHUS, FRVBF_INSN_MADDACCS
+ , FRVBF_INSN_MSUBACCS, FRVBF_INSN_MDADDACCS, FRVBF_INSN_MDSUBACCS, FRVBF_INSN_MASACCS
+ , FRVBF_INSN_MDASACCS, FRVBF_INSN_MMULHS, FRVBF_INSN_MMULHU, FRVBF_INSN_MMULXHS
+ , FRVBF_INSN_MMULXHU, FRVBF_INSN_CMMULHS, FRVBF_INSN_CMMULHU, FRVBF_INSN_MQMULHS
+ , FRVBF_INSN_MQMULHU, FRVBF_INSN_MQMULXHS, FRVBF_INSN_MQMULXHU, FRVBF_INSN_CMQMULHS
+ , FRVBF_INSN_CMQMULHU, FRVBF_INSN_MMACHS, FRVBF_INSN_MMACHU, FRVBF_INSN_MMRDHS
+ , FRVBF_INSN_MMRDHU, FRVBF_INSN_CMMACHS, FRVBF_INSN_CMMACHU, FRVBF_INSN_MQMACHS
+ , FRVBF_INSN_MQMACHU, FRVBF_INSN_CMQMACHS, FRVBF_INSN_CMQMACHU, FRVBF_INSN_MQXMACHS
+ , FRVBF_INSN_MQXMACXHS, FRVBF_INSN_MQMACXHS, FRVBF_INSN_MCPXRS, FRVBF_INSN_MCPXRU
+ , FRVBF_INSN_MCPXIS, FRVBF_INSN_MCPXIU, FRVBF_INSN_CMCPXRS, FRVBF_INSN_CMCPXRU
+ , FRVBF_INSN_CMCPXIS, FRVBF_INSN_CMCPXIU, FRVBF_INSN_MQCPXRS, FRVBF_INSN_MQCPXRU
+ , FRVBF_INSN_MQCPXIS, FRVBF_INSN_MQCPXIU, FRVBF_INSN_MEXPDHW, FRVBF_INSN_CMEXPDHW
+ , FRVBF_INSN_MEXPDHD, FRVBF_INSN_CMEXPDHD, FRVBF_INSN_MPACKH, FRVBF_INSN_MDPACKH
+ , FRVBF_INSN_MUNPACKH, FRVBF_INSN_MDUNPACKH, FRVBF_INSN_MBTOH, FRVBF_INSN_CMBTOH
+ , FRVBF_INSN_MHTOB, FRVBF_INSN_CMHTOB, FRVBF_INSN_MBTOHE, FRVBF_INSN_CMBTOHE
+ , FRVBF_INSN_MNOP, FRVBF_INSN_MCLRACC_0, FRVBF_INSN_MCLRACC_1, FRVBF_INSN_MRDACC
+ , FRVBF_INSN_MRDACCG, FRVBF_INSN_MWTACC, FRVBF_INSN_MWTACCG, FRVBF_INSN_MCOP1
+ , FRVBF_INSN_MCOP2, FRVBF_INSN_FNOP, FRVBF_INSN__MAX
 } FRVBF_INSN_TYPE;
 
 /* Enum declaration for semantic formats in cpu family frvbf.  */
@@ -245,8 +242,7 @@ typedef enum frvbf_sfmt_type {
  , FRVBF_SFMT_LDBFI, FRVBF_SFMT_NLDSBI, FRVBF_SFMT_NLDBFI, FRVBF_SFMT_LDDI
  , FRVBF_SFMT_LDDFI, FRVBF_SFMT_NLDDI, FRVBF_SFMT_NLDDFI, FRVBF_SFMT_LDQI
  , FRVBF_SFMT_LDQFI, FRVBF_SFMT_NLDQFI, FRVBF_SFMT_STB, FRVBF_SFMT_STBF
- , FRVBF_SFMT_STC, FRVBF_SFMT_RSTB, FRVBF_SFMT_RSTBF, FRVBF_SFMT_STD
- , FRVBF_SFMT_STDF, FRVBF_SFMT_STDC, FRVBF_SFMT_RSTD, FRVBF_SFMT_RSTDF
+ , FRVBF_SFMT_STC, FRVBF_SFMT_STD, FRVBF_SFMT_STDF, FRVBF_SFMT_STDC
  , FRVBF_SFMT_STBU, FRVBF_SFMT_STBFU, FRVBF_SFMT_STCU, FRVBF_SFMT_STDU
  , FRVBF_SFMT_STDFU, FRVBF_SFMT_STDCU, FRVBF_SFMT_STQU, FRVBF_SFMT_CLDSB
  , FRVBF_SFMT_CLDBF, FRVBF_SFMT_CLDD, FRVBF_SFMT_CLDDF, FRVBF_SFMT_CLDQ
diff --git a/sim/frv/model.c b/sim/frv/model.c
index 864c180..14c268b 100644
--- a/sim/frv/model.c
+++ b/sim/frv/model.c
@@ -2867,102 +2867,6 @@ model_frv_stc (SIM_CPU *current_cpu, void *sem_arg)
 }
 
 static int
-model_frv_rstb (SIM_CPU *current_cpu, void *sem_arg)
-{
-#define FLD(f) abuf->fields.sfmt_cswap.f
-  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
-  const IDESC * UNUSED idesc = abuf->idesc;
-  int cycles = 0;
-  {
-    int referenced = 0;
-    int UNUSED insn_referenced = abuf->written;
-    cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced);
-  }
-  return cycles;
-#undef FLD
-}
-
-static int
-model_frv_rsth (SIM_CPU *current_cpu, void *sem_arg)
-{
-#define FLD(f) abuf->fields.sfmt_cswap.f
-  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
-  const IDESC * UNUSED idesc = abuf->idesc;
-  int cycles = 0;
-  {
-    int referenced = 0;
-    int UNUSED insn_referenced = abuf->written;
-    cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced);
-  }
-  return cycles;
-#undef FLD
-}
-
-static int
-model_frv_rst (SIM_CPU *current_cpu, void *sem_arg)
-{
-#define FLD(f) abuf->fields.sfmt_cswap.f
-  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
-  const IDESC * UNUSED idesc = abuf->idesc;
-  int cycles = 0;
-  {
-    int referenced = 0;
-    int UNUSED insn_referenced = abuf->written;
-    cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced);
-  }
-  return cycles;
-#undef FLD
-}
-
-static int
-model_frv_rstbf (SIM_CPU *current_cpu, void *sem_arg)
-{
-#define FLD(f) abuf->fields.sfmt_cstbfu.f
-  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
-  const IDESC * UNUSED idesc = abuf->idesc;
-  int cycles = 0;
-  {
-    int referenced = 0;
-    int UNUSED insn_referenced = abuf->written;
-    cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced);
-  }
-  return cycles;
-#undef FLD
-}
-
-static int
-model_frv_rsthf (SIM_CPU *current_cpu, void *sem_arg)
-{
-#define FLD(f) abuf->fields.sfmt_cstbfu.f
-  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
-  const IDESC * UNUSED idesc = abuf->idesc;
-  int cycles = 0;
-  {
-    int referenced = 0;
-    int UNUSED insn_referenced = abuf->written;
-    cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced);
-  }
-  return cycles;
-#undef FLD
-}
-
-static int
-model_frv_rstf (SIM_CPU *current_cpu, void *sem_arg)
-{
-#define FLD(f) abuf->fields.sfmt_cstbfu.f
-  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
-  const IDESC * UNUSED idesc = abuf->idesc;
-  int cycles = 0;
-  {
-    int referenced = 0;
-    int UNUSED insn_referenced = abuf->written;
-    cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced);
-  }
-  return cycles;
-#undef FLD
-}
-
-static int
 model_frv_std (SIM_CPU *current_cpu, void *sem_arg)
 {
 #define FLD(f) abuf->fields.sfmt_cstdu.f
@@ -3011,38 +2915,6 @@ model_frv_stdc (SIM_CPU *current_cpu, void *sem_arg)
 }
 
 static int
-model_frv_rstd (SIM_CPU *current_cpu, void *sem_arg)
-{
-#define FLD(f) abuf->fields.sfmt_cstdu.f
-  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
-  const IDESC * UNUSED idesc = abuf->idesc;
-  int cycles = 0;
-  {
-    int referenced = 0;
-    int UNUSED insn_referenced = abuf->written;
-    cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced);
-  }
-  return cycles;
-#undef FLD
-}
-
-static int
-model_frv_rstdf (SIM_CPU *current_cpu, void *sem_arg)
-{
-#define FLD(f) abuf->fields.sfmt_cstdfu.f
-  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
-  const IDESC * UNUSED idesc = abuf->idesc;
-  int cycles = 0;
-  {
-    int referenced = 0;
-    int UNUSED insn_referenced = abuf->written;
-    cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced);
-  }
-  return cycles;
-#undef FLD
-}
-
-static int
 model_frv_stq (SIM_CPU *current_cpu, void *sem_arg)
 {
 #define FLD(f) abuf->fields.sfmt_smulcc.f
@@ -3091,38 +2963,6 @@ model_frv_stqc (SIM_CPU *current_cpu, void *sem_arg)
 }
 
 static int
-model_frv_rstq (SIM_CPU *current_cpu, void *sem_arg)
-{
-#define FLD(f) abuf->fields.sfmt_smulcc.f
-  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
-  const IDESC * UNUSED idesc = abuf->idesc;
-  int cycles = 0;
-  {
-    int referenced = 0;
-    int UNUSED insn_referenced = abuf->written;
-    cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced);
-  }
-  return cycles;
-#undef FLD
-}
-
-static int
-model_frv_rstqf (SIM_CPU *current_cpu, void *sem_arg)
-{
-#define FLD(f) abuf->fields.sfmt_cstdfu.f
-  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
-  const IDESC * UNUSED idesc = abuf->idesc;
-  int cycles = 0;
-  {
-    int referenced = 0;
-    int UNUSED insn_referenced = abuf->written;
-    cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced);
-  }
-  return cycles;
-#undef FLD
-}
-
-static int
 model_frv_stbu (SIM_CPU *current_cpu, void *sem_arg)
 {
 #define FLD(f) abuf->fields.sfmt_cstbu.f
@@ -16253,102 +16093,6 @@ model_fr550_stc (SIM_CPU *current_cpu, void *sem_arg)
 }
 
 static int
-model_fr550_rstb (SIM_CPU *current_cpu, void *sem_arg)
-{
-#define FLD(f) abuf->fields.sfmt_cswap.f
-  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
-  const IDESC * UNUSED idesc = abuf->idesc;
-  int cycles = 0;
-  {
-    int referenced = 0;
-    int UNUSED insn_referenced = abuf->written;
-    cycles += frvbf_model_fr550_u_exec (current_cpu, idesc, 0, referenced);
-  }
-  return cycles;
-#undef FLD
-}
-
-static int
-model_fr550_rsth (SIM_CPU *current_cpu, void *sem_arg)
-{
-#define FLD(f) abuf->fields.sfmt_cswap.f
-  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
-  const IDESC * UNUSED idesc = abuf->idesc;
-  int cycles = 0;
-  {
-    int referenced = 0;
-    int UNUSED insn_referenced = abuf->written;
-    cycles += frvbf_model_fr550_u_exec (current_cpu, idesc, 0, referenced);
-  }
-  return cycles;
-#undef FLD
-}
-
-static int
-model_fr550_rst (SIM_CPU *current_cpu, void *sem_arg)
-{
-#define FLD(f) abuf->fields.sfmt_cswap.f
-  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
-  const IDESC * UNUSED idesc = abuf->idesc;
-  int cycles = 0;
-  {
-    int referenced = 0;
-    int UNUSED insn_referenced = abuf->written;
-    cycles += frvbf_model_fr550_u_exec (current_cpu, idesc, 0, referenced);
-  }
-  return cycles;
-#undef FLD
-}
-
-static int
-model_fr550_rstbf (SIM_CPU *current_cpu, void *sem_arg)
-{
-#define FLD(f) abuf->fields.sfmt_cstbfu.f
-  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
-  const IDESC * UNUSED idesc = abuf->idesc;
-  int cycles = 0;
-  {
-    int referenced = 0;
-    int UNUSED insn_referenced = abuf->written;
-    cycles += frvbf_model_fr550_u_exec (current_cpu, idesc, 0, referenced);
-  }
-  return cycles;
-#undef FLD
-}
-
-static int
-model_fr550_rsthf (SIM_CPU *current_cpu, void *sem_arg)
-{
-#define FLD(f) abuf->fields.sfmt_cstbfu.f
-  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
-  const IDESC * UNUSED idesc = abuf->idesc;
-  int cycles = 0;
-  {
-    int referenced = 0;
-    int UNUSED insn_referenced = abuf->written;
-    cycles += frvbf_model_fr550_u_exec (current_cpu, idesc, 0, referenced);
-  }
-  return cycles;
-#undef FLD
-}
-
-static int
-model_fr550_rstf (SIM_CPU *current_cpu, void *sem_arg)
-{
-#define FLD(f) abuf->fields.sfmt_cstbfu.f
-  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
-  const IDESC * UNUSED idesc = abuf->idesc;
-  int cycles = 0;
-  {
-    int referenced = 0;
-    int UNUSED insn_referenced = abuf->written;
-    cycles += frvbf_model_fr550_u_exec (current_cpu, idesc, 0, referenced);
-  }
-  return cycles;
-#undef FLD
-}
-
-static int
 model_fr550_std (SIM_CPU *current_cpu, void *sem_arg)
 {
 #define FLD(f) abuf->fields.sfmt_cstdu.f
@@ -16417,38 +16161,6 @@ model_fr550_stdc (SIM_CPU *current_cpu, void *sem_arg)
 }
 
 static int
-model_fr550_rstd (SIM_CPU *current_cpu, void *sem_arg)
-{
-#define FLD(f) abuf->fields.sfmt_cstdu.f
-  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
-  const IDESC * UNUSED idesc = abuf->idesc;
-  int cycles = 0;
-  {
-    int referenced = 0;
-    int UNUSED insn_referenced = abuf->written;
-    cycles += frvbf_model_fr550_u_exec (current_cpu, idesc, 0, referenced);
-  }
-  return cycles;
-#undef FLD
-}
-
-static int
-model_fr550_rstdf (SIM_CPU *current_cpu, void *sem_arg)
-{
-#define FLD(f) abuf->fields.sfmt_cstdfu.f
-  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
-  const IDESC * UNUSED idesc = abuf->idesc;
-  int cycles = 0;
-  {
-    int referenced = 0;
-    int UNUSED insn_referenced = abuf->written;
-    cycles += frvbf_model_fr550_u_exec (current_cpu, idesc, 0, referenced);
-  }
-  return cycles;
-#undef FLD
-}
-
-static int
 model_fr550_stq (SIM_CPU *current_cpu, void *sem_arg)
 {
 #define FLD(f) abuf->fields.sfmt_smulcc.f
@@ -16497,38 +16209,6 @@ model_fr550_stqc (SIM_CPU *current_cpu, void *sem_arg)
 }
 
 static int
-model_fr550_rstq (SIM_CPU *current_cpu, void *sem_arg)
-{
-#define FLD(f) abuf->fields.sfmt_smulcc.f
-  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
-  const IDESC * UNUSED idesc = abuf->idesc;
-  int cycles = 0;
-  {
-    int referenced = 0;
-    int UNUSED insn_referenced = abuf->written;
-    cycles += frvbf_model_fr550_u_exec (current_cpu, idesc, 0, referenced);
-  }
-  return cycles;
-#undef FLD
-}
-
-static int
-model_fr550_rstqf (SIM_CPU *current_cpu, void *sem_arg)
-{
-#define FLD(f) abuf->fields.sfmt_cstdfu.f
-  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
-  const IDESC * UNUSED idesc = abuf->idesc;
-  int cycles = 0;
-  {
-    int referenced = 0;
-    int UNUSED insn_referenced = abuf->written;
-    cycles += frvbf_model_fr550_u_exec (current_cpu, idesc, 0, referenced);
-  }
-  return cycles;
-#undef FLD
-}
-
-static int
 model_fr550_stbu (SIM_CPU *current_cpu, void *sem_arg)
 {
 #define FLD(f) abuf->fields.sfmt_cstbu.f
@@ -33251,162 +32931,6 @@ model_fr500_stc (SIM_CPU *current_cpu, void *sem_arg)
 }
 
 static int
-model_fr500_rstb (SIM_CPU *current_cpu, void *sem_arg)
-{
-#define FLD(f) abuf->fields.sfmt_cswap.f
-  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
-  const IDESC * UNUSED idesc = abuf->idesc;
-  int cycles = 0;
-  {
-    int referenced = 0;
-    int UNUSED insn_referenced = abuf->written;
-    INT in_GRi = -1;
-    INT in_GRj = -1;
-    INT in_GRk = -1;
-    INT in_GRdoublek = -1;
-    in_GRi = FLD (in_GRi);
-    in_GRj = FLD (in_GRj);
-    in_GRk = FLD (in_GRk);
-    referenced |= 1 << 0;
-    referenced |= 1 << 1;
-    referenced |= 1 << 2;
-    cycles += frvbf_model_fr500_u_gr_r_store (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_GRk, in_GRdoublek);
-  }
-  return cycles;
-#undef FLD
-}
-
-static int
-model_fr500_rsth (SIM_CPU *current_cpu, void *sem_arg)
-{
-#define FLD(f) abuf->fields.sfmt_cswap.f
-  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
-  const IDESC * UNUSED idesc = abuf->idesc;
-  int cycles = 0;
-  {
-    int referenced = 0;
-    int UNUSED insn_referenced = abuf->written;
-    INT in_GRi = -1;
-    INT in_GRj = -1;
-    INT in_GRk = -1;
-    INT in_GRdoublek = -1;
-    in_GRi = FLD (in_GRi);
-    in_GRj = FLD (in_GRj);
-    in_GRk = FLD (in_GRk);
-    referenced |= 1 << 0;
-    referenced |= 1 << 1;
-    referenced |= 1 << 2;
-    cycles += frvbf_model_fr500_u_gr_r_store (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_GRk, in_GRdoublek);
-  }
-  return cycles;
-#undef FLD
-}
-
-static int
-model_fr500_rst (SIM_CPU *current_cpu, void *sem_arg)
-{
-#define FLD(f) abuf->fields.sfmt_cswap.f
-  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
-  const IDESC * UNUSED idesc = abuf->idesc;
-  int cycles = 0;
-  {
-    int referenced = 0;
-    int UNUSED insn_referenced = abuf->written;
-    INT in_GRi = -1;
-    INT in_GRj = -1;
-    INT in_GRk = -1;
-    INT in_GRdoublek = -1;
-    in_GRi = FLD (in_GRi);
-    in_GRj = FLD (in_GRj);
-    in_GRk = FLD (in_GRk);
-    referenced |= 1 << 0;
-    referenced |= 1 << 1;
-    referenced |= 1 << 2;
-    cycles += frvbf_model_fr500_u_gr_r_store (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_GRk, in_GRdoublek);
-  }
-  return cycles;
-#undef FLD
-}
-
-static int
-model_fr500_rstbf (SIM_CPU *current_cpu, void *sem_arg)
-{
-#define FLD(f) abuf->fields.sfmt_cstbfu.f
-  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
-  const IDESC * UNUSED idesc = abuf->idesc;
-  int cycles = 0;
-  {
-    int referenced = 0;
-    int UNUSED insn_referenced = abuf->written;
-    INT in_GRi = -1;
-    INT in_GRj = -1;
-    INT in_FRintk = -1;
-    INT in_FRdoublek = -1;
-    in_GRi = FLD (in_GRi);
-    in_GRj = FLD (in_GRj);
-    in_FRintk = FLD (in_FRintk);
-    referenced |= 1 << 0;
-    referenced |= 1 << 1;
-    referenced |= 1 << 2;
-    cycles += frvbf_model_fr500_u_fr_r_store (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_FRintk, in_FRdoublek);
-  }
-  return cycles;
-#undef FLD
-}
-
-static int
-model_fr500_rsthf (SIM_CPU *current_cpu, void *sem_arg)
-{
-#define FLD(f) abuf->fields.sfmt_cstbfu.f
-  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
-  const IDESC * UNUSED idesc = abuf->idesc;
-  int cycles = 0;
-  {
-    int referenced = 0;
-    int UNUSED insn_referenced = abuf->written;
-    INT in_GRi = -1;
-    INT in_GRj = -1;
-    INT in_FRintk = -1;
-    INT in_FRdoublek = -1;
-    in_GRi = FLD (in_GRi);
-    in_GRj = FLD (in_GRj);
-    in_FRintk = FLD (in_FRintk);
-    referenced |= 1 << 0;
-    referenced |= 1 << 1;
-    referenced |= 1 << 2;
-    cycles += frvbf_model_fr500_u_fr_r_store (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_FRintk, in_FRdoublek);
-  }
-  return cycles;
-#undef FLD
-}
-
-static int
-model_fr500_rstf (SIM_CPU *current_cpu, void *sem_arg)
-{
-#define FLD(f) abuf->fields.sfmt_cstbfu.f
-  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
-  const IDESC * UNUSED idesc = abuf->idesc;
-  int cycles = 0;
-  {
-    int referenced = 0;
-    int UNUSED insn_referenced = abuf->written;
-    INT in_GRi = -1;
-    INT in_GRj = -1;
-    INT in_FRintk = -1;
-    INT in_FRdoublek = -1;
-    in_GRi = FLD (in_GRi);
-    in_GRj = FLD (in_GRj);
-    in_FRintk = FLD (in_FRintk);
-    referenced |= 1 << 0;
-    referenced |= 1 << 1;
-    referenced |= 1 << 2;
-    cycles += frvbf_model_fr500_u_fr_r_store (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_FRintk, in_FRdoublek);
-  }
-  return cycles;
-#undef FLD
-}
-
-static int
 model_fr500_std (SIM_CPU *current_cpu, void *sem_arg)
 {
 #define FLD(f) abuf->fields.sfmt_cstdu.f
@@ -33475,58 +32999,6 @@ model_fr500_stdc (SIM_CPU *current_cpu, void *sem_arg)
 }
 
 static int
-model_fr500_rstd (SIM_CPU *current_cpu, void *sem_arg)
-{
-#define FLD(f) abuf->fields.sfmt_cstdu.f
-  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
-  const IDESC * UNUSED idesc = abuf->idesc;
-  int cycles = 0;
-  {
-    int referenced = 0;
-    int UNUSED insn_referenced = abuf->written;
-    INT in_GRi = -1;
-    INT in_GRj = -1;
-    INT in_GRk = -1;
-    INT in_GRdoublek = -1;
-    in_GRi = FLD (in_GRi);
-    in_GRj = FLD (in_GRj);
-    in_GRdoublek = FLD (in_GRdoublek);
-    referenced |= 1 << 0;
-    referenced |= 1 << 1;
-    referenced |= 1 << 3;
-    cycles += frvbf_model_fr500_u_gr_r_store (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_GRk, in_GRdoublek);
-  }
-  return cycles;
-#undef FLD
-}
-
-static int
-model_fr500_rstdf (SIM_CPU *current_cpu, void *sem_arg)
-{
-#define FLD(f) abuf->fields.sfmt_cstdfu.f
-  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
-  const IDESC * UNUSED idesc = abuf->idesc;
-  int cycles = 0;
-  {
-    int referenced = 0;
-    int UNUSED insn_referenced = abuf->written;
-    INT in_GRi = -1;
-    INT in_GRj = -1;
-    INT in_FRintk = -1;
-    INT in_FRdoublek = -1;
-    in_GRi = FLD (in_GRi);
-    in_GRj = FLD (in_GRj);
-    in_FRdoublek = FLD (in_FRdoublek);
-    referenced |= 1 << 0;
-    referenced |= 1 << 1;
-    referenced |= 1 << 3;
-    cycles += frvbf_model_fr500_u_fr_r_store (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_FRintk, in_FRdoublek);
-  }
-  return cycles;
-#undef FLD
-}
-
-static int
 model_fr500_stq (SIM_CPU *current_cpu, void *sem_arg)
 {
 #define FLD(f) abuf->fields.sfmt_smulcc.f
@@ -33591,54 +33063,6 @@ model_fr500_stqc (SIM_CPU *current_cpu, void *sem_arg)
 }
 
 static int
-model_fr500_rstq (SIM_CPU *current_cpu, void *sem_arg)
-{
-#define FLD(f) abuf->fields.sfmt_smulcc.f
-  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
-  const IDESC * UNUSED idesc = abuf->idesc;
-  int cycles = 0;
-  {
-    int referenced = 0;
-    int UNUSED insn_referenced = abuf->written;
-    INT in_GRi = -1;
-    INT in_GRj = -1;
-    INT in_GRk = -1;
-    INT in_GRdoublek = -1;
-    in_GRi = FLD (in_GRi);
-    in_GRj = FLD (in_GRj);
-    referenced |= 1 << 0;
-    referenced |= 1 << 1;
-    cycles += frvbf_model_fr500_u_gr_r_store (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_GRk, in_GRdoublek);
-  }
-  return cycles;
-#undef FLD
-}
-
-static int
-model_fr500_rstqf (SIM_CPU *current_cpu, void *sem_arg)
-{
-#define FLD(f) abuf->fields.sfmt_cstdfu.f
-  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
-  const IDESC * UNUSED idesc = abuf->idesc;
-  int cycles = 0;
-  {
-    int referenced = 0;
-    int UNUSED insn_referenced = abuf->written;
-    INT in_GRi = -1;
-    INT in_GRj = -1;
-    INT in_FRintk = -1;
-    INT in_FRdoublek = -1;
-    in_GRi = FLD (in_GRi);
-    in_GRj = FLD (in_GRj);
-    referenced |= 1 << 0;
-    referenced |= 1 << 1;
-    cycles += frvbf_model_fr500_u_fr_r_store (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_FRintk, in_FRdoublek);
-  }
-  return cycles;
-#undef FLD
-}
-
-static int
 model_fr500_stbu (SIM_CPU *current_cpu, void *sem_arg)
 {
 #define FLD(f) abuf->fields.sfmt_cstbu.f
@@ -49218,102 +48642,6 @@ model_tomcat_stc (SIM_CPU *current_cpu, void *sem_arg)
 }
 
 static int
-model_tomcat_rstb (SIM_CPU *current_cpu, void *sem_arg)
-{
-#define FLD(f) abuf->fields.sfmt_cswap.f
-  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
-  const IDESC * UNUSED idesc = abuf->idesc;
-  int cycles = 0;
-  {
-    int referenced = 0;
-    int UNUSED insn_referenced = abuf->written;
-    cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced);
-  }
-  return cycles;
-#undef FLD
-}
-
-static int
-model_tomcat_rsth (SIM_CPU *current_cpu, void *sem_arg)
-{
-#define FLD(f) abuf->fields.sfmt_cswap.f
-  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
-  const IDESC * UNUSED idesc = abuf->idesc;
-  int cycles = 0;
-  {
-    int referenced = 0;
-    int UNUSED insn_referenced = abuf->written;
-    cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced);
-  }
-  return cycles;
-#undef FLD
-}
-
-static int
-model_tomcat_rst (SIM_CPU *current_cpu, void *sem_arg)
-{
-#define FLD(f) abuf->fields.sfmt_cswap.f
-  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
-  const IDESC * UNUSED idesc = abuf->idesc;
-  int cycles = 0;
-  {
-    int referenced = 0;
-    int UNUSED insn_referenced = abuf->written;
-    cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced);
-  }
-  return cycles;
-#undef FLD
-}
-
-static int
-model_tomcat_rstbf (SIM_CPU *current_cpu, void *sem_arg)
-{
-#define FLD(f) abuf->fields.sfmt_cstbfu.f
-  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
-  const IDESC * UNUSED idesc = abuf->idesc;
-  int cycles = 0;
-  {
-    int referenced = 0;
-    int UNUSED insn_referenced = abuf->written;
-    cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced);
-  }
-  return cycles;
-#undef FLD
-}
-
-static int
-model_tomcat_rsthf (SIM_CPU *current_cpu, void *sem_arg)
-{
-#define FLD(f) abuf->fields.sfmt_cstbfu.f
-  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
-  const IDESC * UNUSED idesc = abuf->idesc;
-  int cycles = 0;
-  {
-    int referenced = 0;
-    int UNUSED insn_referenced = abuf->written;
-    cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced);
-  }
-  return cycles;
-#undef FLD
-}
-
-static int
-model_tomcat_rstf (SIM_CPU *current_cpu, void *sem_arg)
-{
-#define FLD(f) abuf->fields.sfmt_cstbfu.f
-  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
-  const IDESC * UNUSED idesc = abuf->idesc;
-  int cycles = 0;
-  {
-    int referenced = 0;
-    int UNUSED insn_referenced = abuf->written;
-    cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced);
-  }
-  return cycles;
-#undef FLD
-}
-
-static int
 model_tomcat_std (SIM_CPU *current_cpu, void *sem_arg)
 {
 #define FLD(f) abuf->fields.sfmt_cstdu.f
@@ -49362,38 +48690,6 @@ model_tomcat_stdc (SIM_CPU *current_cpu, void *sem_arg)
 }
 
 static int
-model_tomcat_rstd (SIM_CPU *current_cpu, void *sem_arg)
-{
-#define FLD(f) abuf->fields.sfmt_cstdu.f
-  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
-  const IDESC * UNUSED idesc = abuf->idesc;
-  int cycles = 0;
-  {
-    int referenced = 0;
-    int UNUSED insn_referenced = abuf->written;
-    cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced);
-  }
-  return cycles;
-#undef FLD
-}
-
-static int
-model_tomcat_rstdf (SIM_CPU *current_cpu, void *sem_arg)
-{
-#define FLD(f) abuf->fields.sfmt_cstdfu.f
-  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
-  const IDESC * UNUSED idesc = abuf->idesc;
-  int cycles = 0;
-  {
-    int referenced = 0;
-    int UNUSED insn_referenced = abuf->written;
-    cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced);
-  }
-  return cycles;
-#undef FLD
-}
-
-static int
 model_tomcat_stq (SIM_CPU *current_cpu, void *sem_arg)
 {
 #define FLD(f) abuf->fields.sfmt_smulcc.f
@@ -49442,38 +48738,6 @@ model_tomcat_stqc (SIM_CPU *current_cpu, void *sem_arg)
 }
 
 static int
-model_tomcat_rstq (SIM_CPU *current_cpu, void *sem_arg)
-{
-#define FLD(f) abuf->fields.sfmt_smulcc.f
-  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
-  const IDESC * UNUSED idesc = abuf->idesc;
-  int cycles = 0;
-  {
-    int referenced = 0;
-    int UNUSED insn_referenced = abuf->written;
-    cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced);
-  }
-  return cycles;
-#undef FLD
-}
-
-static int
-model_tomcat_rstqf (SIM_CPU *current_cpu, void *sem_arg)
-{
-#define FLD(f) abuf->fields.sfmt_cstdfu.f
-  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
-  const IDESC * UNUSED idesc = abuf->idesc;
-  int cycles = 0;
-  {
-    int referenced = 0;
-    int UNUSED insn_referenced = abuf->written;
-    cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced);
-  }
-  return cycles;
-#undef FLD
-}
-
-static int
 model_tomcat_stbu (SIM_CPU *current_cpu, void *sem_arg)
 {
 #define FLD(f) abuf->fields.sfmt_cstbu.f
@@ -62368,102 +61632,6 @@ model_fr400_stc (SIM_CPU *current_cpu, void *sem_arg)
 }
 
 static int
-model_fr400_rstb (SIM_CPU *current_cpu, void *sem_arg)
-{
-#define FLD(f) abuf->fields.sfmt_cswap.f
-  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
-  const IDESC * UNUSED idesc = abuf->idesc;
-  int cycles = 0;
-  {
-    int referenced = 0;
-    int UNUSED insn_referenced = abuf->written;
-    cycles += frvbf_model_fr400_u_exec (current_cpu, idesc, 0, referenced);
-  }
-  return cycles;
-#undef FLD
-}
-
-static int
-model_fr400_rsth (SIM_CPU *current_cpu, void *sem_arg)
-{
-#define FLD(f) abuf->fields.sfmt_cswap.f
-  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
-  const IDESC * UNUSED idesc = abuf->idesc;
-  int cycles = 0;
-  {
-    int referenced = 0;
-    int UNUSED insn_referenced = abuf->written;
-    cycles += frvbf_model_fr400_u_exec (current_cpu, idesc, 0, referenced);
-  }
-  return cycles;
-#undef FLD
-}
-
-static int
-model_fr400_rst (SIM_CPU *current_cpu, void *sem_arg)
-{
-#define FLD(f) abuf->fields.sfmt_cswap.f
-  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
-  const IDESC * UNUSED idesc = abuf->idesc;
-  int cycles = 0;
-  {
-    int referenced = 0;
-    int UNUSED insn_referenced = abuf->written;
-    cycles += frvbf_model_fr400_u_exec (current_cpu, idesc, 0, referenced);
-  }
-  return cycles;
-#undef FLD
-}
-
-static int
-model_fr400_rstbf (SIM_CPU *current_cpu, void *sem_arg)
-{
-#define FLD(f) abuf->fields.sfmt_cstbfu.f
-  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
-  const IDESC * UNUSED idesc = abuf->idesc;
-  int cycles = 0;
-  {
-    int referenced = 0;
-    int UNUSED insn_referenced = abuf->written;
-    cycles += frvbf_model_fr400_u_exec (current_cpu, idesc, 0, referenced);
-  }
-  return cycles;
-#undef FLD
-}
-
-static int
-model_fr400_rsthf (SIM_CPU *current_cpu, void *sem_arg)
-{
-#define FLD(f) abuf->fields.sfmt_cstbfu.f
-  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
-  const IDESC * UNUSED idesc = abuf->idesc;
-  int cycles = 0;
-  {
-    int referenced = 0;
-    int UNUSED insn_referenced = abuf->written;
-    cycles += frvbf_model_fr400_u_exec (current_cpu, idesc, 0, referenced);
-  }
-  return cycles;
-#undef FLD
-}
-
-static int
-model_fr400_rstf (SIM_CPU *current_cpu, void *sem_arg)
-{
-#define FLD(f) abuf->fields.sfmt_cstbfu.f
-  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
-  const IDESC * UNUSED idesc = abuf->idesc;
-  int cycles = 0;
-  {
-    int referenced = 0;
-    int UNUSED insn_referenced = abuf->written;
-    cycles += frvbf_model_fr400_u_exec (current_cpu, idesc, 0, referenced);
-  }
-  return cycles;
-#undef FLD
-}
-
-static int
 model_fr400_std (SIM_CPU *current_cpu, void *sem_arg)
 {
 #define FLD(f) abuf->fields.sfmt_cstdu.f
@@ -62532,38 +61700,6 @@ model_fr400_stdc (SIM_CPU *current_cpu, void *sem_arg)
 }
 
 static int
-model_fr400_rstd (SIM_CPU *current_cpu, void *sem_arg)
-{
-#define FLD(f) abuf->fields.sfmt_cstdu.f
-  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
-  const IDESC * UNUSED idesc = abuf->idesc;
-  int cycles = 0;
-  {
-    int referenced = 0;
-    int UNUSED insn_referenced = abuf->written;
-    cycles += frvbf_model_fr400_u_exec (current_cpu, idesc, 0, referenced);
-  }
-  return cycles;
-#undef FLD
-}
-
-static int
-model_fr400_rstdf (SIM_CPU *current_cpu, void *sem_arg)
-{
-#define FLD(f) abuf->fields.sfmt_cstdfu.f
-  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
-  const IDESC * UNUSED idesc = abuf->idesc;
-  int cycles = 0;
-  {
-    int referenced = 0;
-    int UNUSED insn_referenced = abuf->written;
-    cycles += frvbf_model_fr400_u_exec (current_cpu, idesc, 0, referenced);
-  }
-  return cycles;
-#undef FLD
-}
-
-static int
 model_fr400_stq (SIM_CPU *current_cpu, void *sem_arg)
 {
 #define FLD(f) abuf->fields.sfmt_smulcc.f
@@ -62612,38 +61748,6 @@ model_fr400_stqc (SIM_CPU *current_cpu, void *sem_arg)
 }
 
 static int
-model_fr400_rstq (SIM_CPU *current_cpu, void *sem_arg)
-{
-#define FLD(f) abuf->fields.sfmt_smulcc.f
-  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
-  const IDESC * UNUSED idesc = abuf->idesc;
-  int cycles = 0;
-  {
-    int referenced = 0;
-    int UNUSED insn_referenced = abuf->written;
-    cycles += frvbf_model_fr400_u_exec (current_cpu, idesc, 0, referenced);
-  }
-  return cycles;
-#undef FLD
-}
-
-static int
-model_fr400_rstqf (SIM_CPU *current_cpu, void *sem_arg)
-{
-#define FLD(f) abuf->fields.sfmt_cstdfu.f
-  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
-  const IDESC * UNUSED idesc = abuf->idesc;
-  int cycles = 0;
-  {
-    int referenced = 0;
-    int UNUSED insn_referenced = abuf->written;
-    cycles += frvbf_model_fr400_u_exec (current_cpu, idesc, 0, referenced);
-  }
-  return cycles;
-#undef FLD
-}
-
-static int
 model_fr400_stbu (SIM_CPU *current_cpu, void *sem_arg)
 {
 #define FLD(f) abuf->fields.sfmt_cstbu.f
@@ -77269,102 +76373,6 @@ model_simple_stc (SIM_CPU *current_cpu, void *sem_arg)
 }
 
 static int
-model_simple_rstb (SIM_CPU *current_cpu, void *sem_arg)
-{
-#define FLD(f) abuf->fields.sfmt_cswap.f
-  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
-  const IDESC * UNUSED idesc = abuf->idesc;
-  int cycles = 0;
-  {
-    int referenced = 0;
-    int UNUSED insn_referenced = abuf->written;
-    cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced);
-  }
-  return cycles;
-#undef FLD
-}
-
-static int
-model_simple_rsth (SIM_CPU *current_cpu, void *sem_arg)
-{
-#define FLD(f) abuf->fields.sfmt_cswap.f
-  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
-  const IDESC * UNUSED idesc = abuf->idesc;
-  int cycles = 0;
-  {
-    int referenced = 0;
-    int UNUSED insn_referenced = abuf->written;
-    cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced);
-  }
-  return cycles;
-#undef FLD
-}
-
-static int
-model_simple_rst (SIM_CPU *current_cpu, void *sem_arg)
-{
-#define FLD(f) abuf->fields.sfmt_cswap.f
-  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
-  const IDESC * UNUSED idesc = abuf->idesc;
-  int cycles = 0;
-  {
-    int referenced = 0;
-    int UNUSED insn_referenced = abuf->written;
-    cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced);
-  }
-  return cycles;
-#undef FLD
-}
-
-static int
-model_simple_rstbf (SIM_CPU *current_cpu, void *sem_arg)
-{
-#define FLD(f) abuf->fields.sfmt_cstbfu.f
-  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
-  const IDESC * UNUSED idesc = abuf->idesc;
-  int cycles = 0;
-  {
-    int referenced = 0;
-    int UNUSED insn_referenced = abuf->written;
-    cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced);
-  }
-  return cycles;
-#undef FLD
-}
-
-static int
-model_simple_rsthf (SIM_CPU *current_cpu, void *sem_arg)
-{
-#define FLD(f) abuf->fields.sfmt_cstbfu.f
-  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
-  const IDESC * UNUSED idesc = abuf->idesc;
-  int cycles = 0;
-  {
-    int referenced = 0;
-    int UNUSED insn_referenced = abuf->written;
-    cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced);
-  }
-  return cycles;
-#undef FLD
-}
-
-static int
-model_simple_rstf (SIM_CPU *current_cpu, void *sem_arg)
-{
-#define FLD(f) abuf->fields.sfmt_cstbfu.f
-  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
-  const IDESC * UNUSED idesc = abuf->idesc;
-  int cycles = 0;
-  {
-    int referenced = 0;
-    int UNUSED insn_referenced = abuf->written;
-    cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced);
-  }
-  return cycles;
-#undef FLD
-}
-
-static int
 model_simple_std (SIM_CPU *current_cpu, void *sem_arg)
 {
 #define FLD(f) abuf->fields.sfmt_cstdu.f
@@ -77413,38 +76421,6 @@ model_simple_stdc (SIM_CPU *current_cpu, void *sem_arg)
 }
 
 static int
-model_simple_rstd (SIM_CPU *current_cpu, void *sem_arg)
-{
-#define FLD(f) abuf->fields.sfmt_cstdu.f
-  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
-  const IDESC * UNUSED idesc = abuf->idesc;
-  int cycles = 0;
-  {
-    int referenced = 0;
-    int UNUSED insn_referenced = abuf->written;
-    cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced);
-  }
-  return cycles;
-#undef FLD
-}
-
-static int
-model_simple_rstdf (SIM_CPU *current_cpu, void *sem_arg)
-{
-#define FLD(f) abuf->fields.sfmt_cstdfu.f
-  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
-  const IDESC * UNUSED idesc = abuf->idesc;
-  int cycles = 0;
-  {
-    int referenced = 0;
-    int UNUSED insn_referenced = abuf->written;
-    cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced);
-  }
-  return cycles;
-#undef FLD
-}
-
-static int
 model_simple_stq (SIM_CPU *current_cpu, void *sem_arg)
 {
 #define FLD(f) abuf->fields.sfmt_smulcc.f
@@ -77493,38 +76469,6 @@ model_simple_stqc (SIM_CPU *current_cpu, void *sem_arg)
 }
 
 static int
-model_simple_rstq (SIM_CPU *current_cpu, void *sem_arg)
-{
-#define FLD(f) abuf->fields.sfmt_smulcc.f
-  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
-  const IDESC * UNUSED idesc = abuf->idesc;
-  int cycles = 0;
-  {
-    int referenced = 0;
-    int UNUSED insn_referenced = abuf->written;
-    cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced);
-  }
-  return cycles;
-#undef FLD
-}
-
-static int
-model_simple_rstqf (SIM_CPU *current_cpu, void *sem_arg)
-{
-#define FLD(f) abuf->fields.sfmt_cstdfu.f
-  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
-  const IDESC * UNUSED idesc = abuf->idesc;
-  int cycles = 0;
-  {
-    int referenced = 0;
-    int UNUSED insn_referenced = abuf->written;
-    cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced);
-  }
-  return cycles;
-#undef FLD
-}
-
-static int
 model_simple_stbu (SIM_CPU *current_cpu, void *sem_arg)
 {
 #define FLD(f) abuf->fields.sfmt_cstbu.f
@@ -86561,22 +85505,12 @@ static const INSN_TIMING frv_timing[] = {
   { FRVBF_INSN_STHF, model_frv_sthf, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } },
   { FRVBF_INSN_STF, model_frv_stf, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } },
   { FRVBF_INSN_STC, model_frv_stc, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } },
-  { FRVBF_INSN_RSTB, model_frv_rstb, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } },
-  { FRVBF_INSN_RSTH, model_frv_rsth, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } },
-  { FRVBF_INSN_RST, model_frv_rst, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } },
-  { FRVBF_INSN_RSTBF, model_frv_rstbf, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } },
-  { FRVBF_INSN_RSTHF, model_frv_rsthf, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } },
-  { FRVBF_INSN_RSTF, model_frv_rstf, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } },
   { FRVBF_INSN_STD, model_frv_std, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } },
   { FRVBF_INSN_STDF, model_frv_stdf, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } },
   { FRVBF_INSN_STDC, model_frv_stdc, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } },
-  { FRVBF_INSN_RSTD, model_frv_rstd, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } },
-  { FRVBF_INSN_RSTDF, model_frv_rstdf, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } },
   { FRVBF_INSN_STQ, model_frv_stq, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } },
   { FRVBF_INSN_STQF, model_frv_stqf, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } },
   { FRVBF_INSN_STQC, model_frv_stqc, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } },
-  { FRVBF_INSN_RSTQ, model_frv_rstq, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } },
-  { FRVBF_INSN_RSTQF, model_frv_rstqf, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } },
   { FRVBF_INSN_STBU, model_frv_stbu, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } },
   { FRVBF_INSN_STHU, model_frv_sthu, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } },
   { FRVBF_INSN_STU, model_frv_stu, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } },
@@ -87318,22 +86252,12 @@ static const INSN_TIMING fr550_timing[] = {
   { FRVBF_INSN_STHF, model_fr550_sthf, { { (int) UNIT_FR550_U_FR_STORE, 1, 1 } } },
   { FRVBF_INSN_STF, model_fr550_stf, { { (int) UNIT_FR550_U_FR_STORE, 1, 1 } } },
   { FRVBF_INSN_STC, model_fr550_stc, { { (int) UNIT_FR550_U_EXEC, 1, 1 } } },
-  { FRVBF_INSN_RSTB, model_fr550_rstb, { { (int) UNIT_FR550_U_EXEC, 1, 1 } } },
-  { FRVBF_INSN_RSTH, model_fr550_rsth, { { (int) UNIT_FR550_U_EXEC, 1, 1 } } },
-  { FRVBF_INSN_RST, model_fr550_rst, { { (int) UNIT_FR550_U_EXEC, 1, 1 } } },
-  { FRVBF_INSN_RSTBF, model_fr550_rstbf, { { (int) UNIT_FR550_U_EXEC, 1, 1 } } },
-  { FRVBF_INSN_RSTHF, model_fr550_rsthf, { { (int) UNIT_FR550_U_EXEC, 1, 1 } } },
-  { FRVBF_INSN_RSTF, model_fr550_rstf, { { (int) UNIT_FR550_U_EXEC, 1, 1 } } },
   { FRVBF_INSN_STD, model_fr550_std, { { (int) UNIT_FR550_U_GR_STORE, 1, 1 } } },
   { FRVBF_INSN_STDF, model_fr550_stdf, { { (int) UNIT_FR550_U_FR_STORE, 1, 1 } } },
   { FRVBF_INSN_STDC, model_fr550_stdc, { { (int) UNIT_FR550_U_EXEC, 1, 1 } } },
-  { FRVBF_INSN_RSTD, model_fr550_rstd, { { (int) UNIT_FR550_U_EXEC, 1, 1 } } },
-  { FRVBF_INSN_RSTDF, model_fr550_rstdf, { { (int) UNIT_FR550_U_EXEC, 1, 1 } } },
   { FRVBF_INSN_STQ, model_fr550_stq, { { (int) UNIT_FR550_U_EXEC, 1, 1 } } },
   { FRVBF_INSN_STQF, model_fr550_stqf, { { (int) UNIT_FR550_U_EXEC, 1, 1 } } },
   { FRVBF_INSN_STQC, model_fr550_stqc, { { (int) UNIT_FR550_U_EXEC, 1, 1 } } },
-  { FRVBF_INSN_RSTQ, model_fr550_rstq, { { (int) UNIT_FR550_U_EXEC, 1, 1 } } },
-  { FRVBF_INSN_RSTQF, model_fr550_rstqf, { { (int) UNIT_FR550_U_EXEC, 1, 1 } } },
   { FRVBF_INSN_STBU, model_fr550_stbu, { { (int) UNIT_FR550_U_GR_STORE, 1, 1 } } },
   { FRVBF_INSN_STHU, model_fr550_sthu, { { (int) UNIT_FR550_U_GR_STORE, 1, 1 } } },
   { FRVBF_INSN_STU, model_fr550_stu, { { (int) UNIT_FR550_U_GR_STORE, 1, 1 } } },
@@ -88075,22 +86999,12 @@ static const INSN_TIMING fr500_timing[] = {
   { FRVBF_INSN_STHF, model_fr500_sthf, { { (int) UNIT_FR500_U_FR_STORE, 1, 1 } } },
   { FRVBF_INSN_STF, model_fr500_stf, { { (int) UNIT_FR500_U_FR_STORE, 1, 1 } } },
   { FRVBF_INSN_STC, model_fr500_stc, { { (int) UNIT_FR500_U_EXEC, 1, 1 } } },
-  { FRVBF_INSN_RSTB, model_fr500_rstb, { { (int) UNIT_FR500_U_GR_R_STORE, 1, 1 } } },
-  { FRVBF_INSN_RSTH, model_fr500_rsth, { { (int) UNIT_FR500_U_GR_R_STORE, 1, 1 } } },
-  { FRVBF_INSN_RST, model_fr500_rst, { { (int) UNIT_FR500_U_GR_R_STORE, 1, 1 } } },
-  { FRVBF_INSN_RSTBF, model_fr500_rstbf, { { (int) UNIT_FR500_U_FR_R_STORE, 1, 1 } } },
-  { FRVBF_INSN_RSTHF, model_fr500_rsthf, { { (int) UNIT_FR500_U_FR_R_STORE, 1, 1 } } },
-  { FRVBF_INSN_RSTF, model_fr500_rstf, { { (int) UNIT_FR500_U_FR_R_STORE, 1, 1 } } },
   { FRVBF_INSN_STD, model_fr500_std, { { (int) UNIT_FR500_U_GR_STORE, 1, 1 } } },
   { FRVBF_INSN_STDF, model_fr500_stdf, { { (int) UNIT_FR500_U_FR_STORE, 1, 1 } } },
   { FRVBF_INSN_STDC, model_fr500_stdc, { { (int) UNIT_FR500_U_EXEC, 1, 1 } } },
-  { FRVBF_INSN_RSTD, model_fr500_rstd, { { (int) UNIT_FR500_U_GR_R_STORE, 1, 1 } } },
-  { FRVBF_INSN_RSTDF, model_fr500_rstdf, { { (int) UNIT_FR500_U_FR_R_STORE, 1, 1 } } },
   { FRVBF_INSN_STQ, model_fr500_stq, { { (int) UNIT_FR500_U_GR_STORE, 1, 1 } } },
   { FRVBF_INSN_STQF, model_fr500_stqf, { { (int) UNIT_FR500_U_FR_STORE, 1, 1 } } },
   { FRVBF_INSN_STQC, model_fr500_stqc, { { (int) UNIT_FR500_U_EXEC, 1, 1 } } },
-  { FRVBF_INSN_RSTQ, model_fr500_rstq, { { (int) UNIT_FR500_U_GR_R_STORE, 1, 1 } } },
-  { FRVBF_INSN_RSTQF, model_fr500_rstqf, { { (int) UNIT_FR500_U_FR_R_STORE, 1, 1 } } },
   { FRVBF_INSN_STBU, model_fr500_stbu, { { (int) UNIT_FR500_U_GR_STORE, 1, 1 } } },
   { FRVBF_INSN_STHU, model_fr500_sthu, { { (int) UNIT_FR500_U_GR_STORE, 1, 1 } } },
   { FRVBF_INSN_STU, model_fr500_stu, { { (int) UNIT_FR500_U_GR_STORE, 1, 1 } } },
@@ -88832,22 +87746,12 @@ static const INSN_TIMING tomcat_timing[] = {
   { FRVBF_INSN_STHF, model_tomcat_sthf, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } },
   { FRVBF_INSN_STF, model_tomcat_stf, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } },
   { FRVBF_INSN_STC, model_tomcat_stc, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } },
-  { FRVBF_INSN_RSTB, model_tomcat_rstb, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } },
-  { FRVBF_INSN_RSTH, model_tomcat_rsth, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } },
-  { FRVBF_INSN_RST, model_tomcat_rst, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } },
-  { FRVBF_INSN_RSTBF, model_tomcat_rstbf, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } },
-  { FRVBF_INSN_RSTHF, model_tomcat_rsthf, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } },
-  { FRVBF_INSN_RSTF, model_tomcat_rstf, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } },
   { FRVBF_INSN_STD, model_tomcat_std, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } },
   { FRVBF_INSN_STDF, model_tomcat_stdf, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } },
   { FRVBF_INSN_STDC, model_tomcat_stdc, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } },
-  { FRVBF_INSN_RSTD, model_tomcat_rstd, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } },
-  { FRVBF_INSN_RSTDF, model_tomcat_rstdf, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } },
   { FRVBF_INSN_STQ, model_tomcat_stq, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } },
   { FRVBF_INSN_STQF, model_tomcat_stqf, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } },
   { FRVBF_INSN_STQC, model_tomcat_stqc, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } },
-  { FRVBF_INSN_RSTQ, model_tomcat_rstq, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } },
-  { FRVBF_INSN_RSTQF, model_tomcat_rstqf, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } },
   { FRVBF_INSN_STBU, model_tomcat_stbu, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } },
   { FRVBF_INSN_STHU, model_tomcat_sthu, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } },
   { FRVBF_INSN_STU, model_tomcat_stu, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } },
@@ -89589,22 +88493,12 @@ static const INSN_TIMING fr400_timing[] = {
   { FRVBF_INSN_STHF, model_fr400_sthf, { { (int) UNIT_FR400_U_FR_STORE, 1, 1 } } },
   { FRVBF_INSN_STF, model_fr400_stf, { { (int) UNIT_FR400_U_FR_STORE, 1, 1 } } },
   { FRVBF_INSN_STC, model_fr400_stc, { { (int) UNIT_FR400_U_EXEC, 1, 1 } } },
-  { FRVBF_INSN_RSTB, model_fr400_rstb, { { (int) UNIT_FR400_U_EXEC, 1, 1 } } },
-  { FRVBF_INSN_RSTH, model_fr400_rsth, { { (int) UNIT_FR400_U_EXEC, 1, 1 } } },
-  { FRVBF_INSN_RST, model_fr400_rst, { { (int) UNIT_FR400_U_EXEC, 1, 1 } } },
-  { FRVBF_INSN_RSTBF, model_fr400_rstbf, { { (int) UNIT_FR400_U_EXEC, 1, 1 } } },
-  { FRVBF_INSN_RSTHF, model_fr400_rsthf, { { (int) UNIT_FR400_U_EXEC, 1, 1 } } },
-  { FRVBF_INSN_RSTF, model_fr400_rstf, { { (int) UNIT_FR400_U_EXEC, 1, 1 } } },
   { FRVBF_INSN_STD, model_fr400_std, { { (int) UNIT_FR400_U_GR_STORE, 1, 1 } } },
   { FRVBF_INSN_STDF, model_fr400_stdf, { { (int) UNIT_FR400_U_FR_STORE, 1, 1 } } },
   { FRVBF_INSN_STDC, model_fr400_stdc, { { (int) UNIT_FR400_U_EXEC, 1, 1 } } },
-  { FRVBF_INSN_RSTD, model_fr400_rstd, { { (int) UNIT_FR400_U_EXEC, 1, 1 } } },
-  { FRVBF_INSN_RSTDF, model_fr400_rstdf, { { (int) UNIT_FR400_U_EXEC, 1, 1 } } },
   { FRVBF_INSN_STQ, model_fr400_stq, { { (int) UNIT_FR400_U_EXEC, 1, 1 } } },
   { FRVBF_INSN_STQF, model_fr400_stqf, { { (int) UNIT_FR400_U_EXEC, 1, 1 } } },
   { FRVBF_INSN_STQC, model_fr400_stqc, { { (int) UNIT_FR400_U_EXEC, 1, 1 } } },
-  { FRVBF_INSN_RSTQ, model_fr400_rstq, { { (int) UNIT_FR400_U_EXEC, 1, 1 } } },
-  { FRVBF_INSN_RSTQF, model_fr400_rstqf, { { (int) UNIT_FR400_U_EXEC, 1, 1 } } },
   { FRVBF_INSN_STBU, model_fr400_stbu, { { (int) UNIT_FR400_U_GR_STORE, 1, 1 } } },
   { FRVBF_INSN_STHU, model_fr400_sthu, { { (int) UNIT_FR400_U_GR_STORE, 1, 1 } } },
   { FRVBF_INSN_STU, model_fr400_stu, { { (int) UNIT_FR400_U_GR_STORE, 1, 1 } } },
@@ -90346,22 +89240,12 @@ static const INSN_TIMING simple_timing[] = {
   { FRVBF_INSN_STHF, model_simple_sthf, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } },
   { FRVBF_INSN_STF, model_simple_stf, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } },
   { FRVBF_INSN_STC, model_simple_stc, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } },
-  { FRVBF_INSN_RSTB, model_simple_rstb, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } },
-  { FRVBF_INSN_RSTH, model_simple_rsth, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } },
-  { FRVBF_INSN_RST, model_simple_rst, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } },
-  { FRVBF_INSN_RSTBF, model_simple_rstbf, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } },
-  { FRVBF_INSN_RSTHF, model_simple_rsthf, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } },
-  { FRVBF_INSN_RSTF, model_simple_rstf, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } },
   { FRVBF_INSN_STD, model_simple_std, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } },
   { FRVBF_INSN_STDF, model_simple_stdf, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } },
   { FRVBF_INSN_STDC, model_simple_stdc, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } },
-  { FRVBF_INSN_RSTD, model_simple_rstd, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } },
-  { FRVBF_INSN_RSTDF, model_simple_rstdf, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } },
   { FRVBF_INSN_STQ, model_simple_stq, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } },
   { FRVBF_INSN_STQF, model_simple_stqf, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } },
   { FRVBF_INSN_STQC, model_simple_stqc, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } },
-  { FRVBF_INSN_RSTQ, model_simple_rstq, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } },
-  { FRVBF_INSN_RSTQF, model_simple_rstqf, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } },
   { FRVBF_INSN_STBU, model_simple_stbu, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } },
   { FRVBF_INSN_STHU, model_simple_sthu, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } },
   { FRVBF_INSN_STU, model_simple_stu, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } },
diff --git a/sim/frv/sem.c b/sim/frv/sem.c
index 4f2883b..063717e 100644
--- a/sim/frv/sem.c
+++ b/sim/frv/sem.c
@@ -5630,138 +5630,6 @@ frvbf_write_mem_SI (current_cpu, pc, ADDSI (GET_H_GR (FLD (f_GRi)), GET_H_GR (FL
 #undef FLD
 }
 
-/* rstb: rstb$pack $GRk,@($GRi,$GRj) */
-
-static SEM_PC
-SEM_FN_NAME (frvbf,rstb) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
-{
-#define FLD(f) abuf->fields.sfmt_cswap.f
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
-
-{
-  SI tmp_address;
-  tmp_address = ADDSI (GET_H_GR (FLD (f_GRi)), GET_H_GR (FLD (f_GRj)));
-frvbf_write_mem_QI (current_cpu, pc, tmp_address, GET_H_GR (FLD (f_GRk)));
-frvbf_check_recovering_store (current_cpu, tmp_address, FLD (f_GRk), 1, 0);
-}
-
-  return vpc;
-#undef FLD
-}
-
-/* rsth: rsth$pack $GRk,@($GRi,$GRj) */
-
-static SEM_PC
-SEM_FN_NAME (frvbf,rsth) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
-{
-#define FLD(f) abuf->fields.sfmt_cswap.f
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
-
-{
-  SI tmp_address;
-  tmp_address = ADDSI (GET_H_GR (FLD (f_GRi)), GET_H_GR (FLD (f_GRj)));
-frvbf_write_mem_HI (current_cpu, pc, tmp_address, GET_H_GR (FLD (f_GRk)));
-frvbf_check_recovering_store (current_cpu, tmp_address, FLD (f_GRk), 2, 0);
-}
-
-  return vpc;
-#undef FLD
-}
-
-/* rst: rst$pack $GRk,@($GRi,$GRj) */
-
-static SEM_PC
-SEM_FN_NAME (frvbf,rst) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
-{
-#define FLD(f) abuf->fields.sfmt_cswap.f
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
-
-{
-  SI tmp_address;
-  tmp_address = ADDSI (GET_H_GR (FLD (f_GRi)), GET_H_GR (FLD (f_GRj)));
-frvbf_write_mem_SI (current_cpu, pc, tmp_address, GET_H_GR (FLD (f_GRk)));
-frvbf_check_recovering_store (current_cpu, tmp_address, FLD (f_GRk), 4, 0);
-}
-
-  return vpc;
-#undef FLD
-}
-
-/* rstbf: rstbf$pack $FRintk,@($GRi,$GRj) */
-
-static SEM_PC
-SEM_FN_NAME (frvbf,rstbf) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
-{
-#define FLD(f) abuf->fields.sfmt_cstbfu.f
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
-
-{
-  SI tmp_address;
-  tmp_address = ADDSI (GET_H_GR (FLD (f_GRi)), GET_H_GR (FLD (f_GRj)));
-frvbf_write_mem_QI (current_cpu, pc, tmp_address, GET_H_FR_INT (FLD (f_FRk)));
-frvbf_check_recovering_store (current_cpu, tmp_address, FLD (f_FRk), 1, 1);
-}
-
-  return vpc;
-#undef FLD
-}
-
-/* rsthf: rsthf$pack $FRintk,@($GRi,$GRj) */
-
-static SEM_PC
-SEM_FN_NAME (frvbf,rsthf) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
-{
-#define FLD(f) abuf->fields.sfmt_cstbfu.f
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
-
-{
-  SI tmp_address;
-  tmp_address = ADDSI (GET_H_GR (FLD (f_GRi)), GET_H_GR (FLD (f_GRj)));
-frvbf_write_mem_HI (current_cpu, pc, tmp_address, GET_H_FR_INT (FLD (f_FRk)));
-frvbf_check_recovering_store (current_cpu, tmp_address, FLD (f_FRk), 2, 1);
-}
-
-  return vpc;
-#undef FLD
-}
-
-/* rstf: rstf$pack $FRintk,@($GRi,$GRj) */
-
-static SEM_PC
-SEM_FN_NAME (frvbf,rstf) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
-{
-#define FLD(f) abuf->fields.sfmt_cstbfu.f
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
-
-{
-  SI tmp_address;
-  tmp_address = ADDSI (GET_H_GR (FLD (f_GRi)), GET_H_GR (FLD (f_GRj)));
-frvbf_write_mem_SI (current_cpu, pc, tmp_address, GET_H_FR_INT (FLD (f_FRk)));
-frvbf_check_recovering_store (current_cpu, tmp_address, FLD (f_FRk), 4, 1);
-}
-
-  return vpc;
-#undef FLD
-}
-
 /* std: std$pack $GRdoublek,@($GRi,$GRj) */
 
 static SEM_PC
@@ -5831,54 +5699,6 @@ frvbf_write_mem_DI (current_cpu, pc, tmp_address, GET_H_CPR_DOUBLE (FLD (f_CPRk)
 #undef FLD
 }
 
-/* rstd: rstd$pack $GRdoublek,@($GRi,$GRj) */
-
-static SEM_PC
-SEM_FN_NAME (frvbf,rstd) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
-{
-#define FLD(f) abuf->fields.sfmt_cstdu.f
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
-
-{
-  SI tmp_address;
-{
-  tmp_address = ADDSI (GET_H_GR (FLD (f_GRi)), GET_H_GR (FLD (f_GRj)));
-frvbf_write_mem_DI (current_cpu, pc, tmp_address, GET_H_GR_DOUBLE (FLD (f_GRk)));
-}
-frvbf_check_recovering_store (current_cpu, tmp_address, FLD (f_GRk), 8, 0);
-}
-
-  return vpc;
-#undef FLD
-}
-
-/* rstdf: rstdf$pack $FRdoublek,@($GRi,$GRj) */
-
-static SEM_PC
-SEM_FN_NAME (frvbf,rstdf) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
-{
-#define FLD(f) abuf->fields.sfmt_cstdfu.f
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
-
-{
-  SI tmp_address;
-{
-  tmp_address = ADDSI (GET_H_GR (FLD (f_GRi)), GET_H_GR (FLD (f_GRj)));
-frvbf_write_mem_DF (current_cpu, pc, tmp_address, GET_H_FR_DOUBLE (FLD (f_FRk)));
-}
-frvbf_check_recovering_store (current_cpu, tmp_address, FLD (f_FRk), 8, 1);
-}
-
-  return vpc;
-#undef FLD
-}
-
 /* stq: stq$pack $GRk,@($GRi,$GRj) */
 
 static SEM_PC
@@ -5948,54 +5768,6 @@ frvbf_store_quad_CPR (current_cpu, pc, tmp_address, FLD (f_CPRk));
 #undef FLD
 }
 
-/* rstq: rstq$pack $GRk,@($GRi,$GRj) */
-
-static SEM_PC
-SEM_FN_NAME (frvbf,rstq) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
-{
-#define FLD(f) abuf->fields.sfmt_smulcc.f
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
-
-{
-  SI tmp_address;
-{
-  tmp_address = ADDSI (GET_H_GR (FLD (f_GRi)), GET_H_GR (FLD (f_GRj)));
-frvbf_store_quad_GR (current_cpu, pc, tmp_address, FLD (f_GRk));
-}
-frvbf_check_recovering_store (current_cpu, tmp_address, FLD (f_GRk), 16, 0);
-}
-
-  return vpc;
-#undef FLD
-}
-
-/* rstqf: rstqf$pack $FRintk,@($GRi,$GRj) */
-
-static SEM_PC
-SEM_FN_NAME (frvbf,rstqf) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
-{
-#define FLD(f) abuf->fields.sfmt_cstdfu.f
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
-
-{
-  SI tmp_address;
-{
-  tmp_address = ADDSI (GET_H_GR (FLD (f_GRi)), GET_H_GR (FLD (f_GRj)));
-frvbf_store_quad_FRint (current_cpu, pc, tmp_address, FLD (f_FRk));
-}
-frvbf_check_recovering_store (current_cpu, tmp_address, FLD (f_FRk), 16, 1);
-}
-
-  return vpc;
-#undef FLD
-}
-
 /* stbu: stbu$pack $GRk,@($GRi,$GRj) */
 
 static SEM_PC
@@ -28264,22 +28036,12 @@ static const struct sem_fn_desc sem_fns[] = {
   { FRVBF_INSN_STHF, SEM_FN_NAME (frvbf,sthf) },
   { FRVBF_INSN_STF, SEM_FN_NAME (frvbf,stf) },
   { FRVBF_INSN_STC, SEM_FN_NAME (frvbf,stc) },
-  { FRVBF_INSN_RSTB, SEM_FN_NAME (frvbf,rstb) },
-  { FRVBF_INSN_RSTH, SEM_FN_NAME (frvbf,rsth) },
-  { FRVBF_INSN_RST, SEM_FN_NAME (frvbf,rst) },
-  { FRVBF_INSN_RSTBF, SEM_FN_NAME (frvbf,rstbf) },
-  { FRVBF_INSN_RSTHF, SEM_FN_NAME (frvbf,rsthf) },
-  { FRVBF_INSN_RSTF, SEM_FN_NAME (frvbf,rstf) },
   { FRVBF_INSN_STD, SEM_FN_NAME (frvbf,std) },
   { FRVBF_INSN_STDF, SEM_FN_NAME (frvbf,stdf) },
   { FRVBF_INSN_STDC, SEM_FN_NAME (frvbf,stdc) },
-  { FRVBF_INSN_RSTD, SEM_FN_NAME (frvbf,rstd) },
-  { FRVBF_INSN_RSTDF, SEM_FN_NAME (frvbf,rstdf) },
   { FRVBF_INSN_STQ, SEM_FN_NAME (frvbf,stq) },
   { FRVBF_INSN_STQF, SEM_FN_NAME (frvbf,stqf) },
   { FRVBF_INSN_STQC, SEM_FN_NAME (frvbf,stqc) },
-  { FRVBF_INSN_RSTQ, SEM_FN_NAME (frvbf,rstq) },
-  { FRVBF_INSN_RSTQF, SEM_FN_NAME (frvbf,rstqf) },
   { FRVBF_INSN_STBU, SEM_FN_NAME (frvbf,stbu) },
   { FRVBF_INSN_STHU, SEM_FN_NAME (frvbf,sthu) },
   { FRVBF_INSN_STU, SEM_FN_NAME (frvbf,stu) },
diff --git a/sim/testsuite/ChangeLog b/sim/testsuite/ChangeLog
index 4e7b230..32e71da 100644
--- a/sim/testsuite/ChangeLog
+++ b/sim/testsuite/ChangeLog
@@ -1,3 +1,8 @@
+2004-03-01  Richard Sandiford  <rsandifo@redhat.com>
+
+	* sim/frv/{rstb,rsth,rst,rstd,rstq}.cgs: Delete.
+	* sim/frv/{rstbf,rsthf,rstf,rstdf,rstqf}.cgs: Delete.
+
 2004-01-26  Chris Demetriou  <cgd@broadcom.com>
 
 	* sim/mips: New directory.  Tests for the MIPS simulator.
diff --git a/sim/testsuite/sim/frv/rst.cgs b/sim/testsuite/sim/frv/rst.cgs
deleted file mode 100644
index c8ba442..0000000
--- a/sim/testsuite/sim/frv/rst.cgs
+++ /dev/null
@@ -1,107 +0,0 @@
-# frv testcase for rst $GRk,@($GRi,$GRj)
-# mach: frv
-# as(frv): -mcpu=frv
-
-	.include "testutils.inc"
-
-	start
-
-	.global rst
-rst:
-	; No nesr's active
-	set_gr_gr	sp,gr10
-	set_gr_gr	sp,gr24
-	set_mem_limmed	0x2222,0x2222,gr24
-	set_gr_gr	gr24,gr27
-	inc_gr_immed	-4,gr27
-	set_mem_limmed	0x3333,0x3333,gr27
-	set_gr_gr	gr27,gr26
-	inc_gr_immed	-4,gr26
-	set_mem_limmed	0x4444,0x4444,gr26
-	set_gr_gr	gr26,gr25
-	inc_gr_immed	-4,gr25
-	set_mem_limmed	0x5555,0x5555,gr25
-	set_gr_limmed	0x1111,0x1111,gr20
-	set_gr_immed	0,gr7
-	set_gr_limmed	0xffff,0xffff,gr8
-	rst		gr8,@(sp,gr7)
-	test_mem_limmed	0xffff,0xffff,gr24
-	test_mem_limmed	0x3333,0x3333,gr27
-	test_mem_limmed	0x4444,0x4444,gr26
-	test_mem_limmed	0x5555,0x5555,gr25
-	test_gr_limmed	0x1111,0x1111,gr20
-
-	; 1 nesr active with the incorrect address in neear for gr
-	nldi		@(sp,0),gr20
-	test_spr_gr	neear0,gr10
-	set_mem_limmed	0x2222,0x2222,gr24
-	set_mem_limmed	0x3333,0x3333,gr27
-	set_mem_limmed	0x4444,0x4444,gr26
-	set_mem_limmed	0x5555,0x5555,gr25
-	set_gr_limmed	0x1111,0x1111,gr20
-	set_gr_limmed	0xffff,0xffff,gr8
-	set_gr_immed	-4,gr7
-	rst		gr8,@(sp,gr7)
-	test_mem_limmed	0x2222,0x2222,gr24
-	test_mem_limmed	0xffff,0xffff,gr27
-	test_mem_limmed	0x4444,0x4444,gr26
-	test_mem_limmed	0x5555,0x5555,gr25
-	test_gr_limmed	0x1111,0x1111,gr20
-
-	; 1 nesr active with the incorrect address in neear for fr
-	inc_gr_immed	-4,gr10
-	nldfi		@(sp,-4),fr20
-	test_spr_gr	neear1,gr10
-	set_mem_limmed	0x2222,0x2222,gr24
-	set_mem_limmed	0x3333,0x3333,gr27
-	set_mem_limmed	0x4444,0x4444,gr26
-	set_mem_limmed	0x5555,0x5555,gr25
-	set_fr_iimmed	0x1111,0x1111,fr20
-	set_gr_limmed	0xffff,0xffff,gr8
-	inc_gr_immed	-4,sp
-	set_gr_immed	4,gr7
-	rst		gr8,@(sp,gr7)
-	test_mem_limmed	0xffff,0xffff,gr24
-	test_mem_limmed	0x3333,0x3333,gr27
-	test_mem_limmed	0x4444,0x4444,gr26
-	test_mem_limmed	0x5555,0x5555,gr25
-	test_fr_limmed	0x1111,0x1111,fr20
-
-	; 1 nesr active with the correct address in neear for gr
-	inc_gr_immed	-4,gr10
-	nldi		@(sp,-4),gr20
-	test_spr_gr	neear2,gr10
-	set_mem_limmed	0x2222,0x2222,gr24
-	set_mem_limmed	0x3333,0x3333,gr27
-	set_mem_limmed	0x4444,0x4444,gr26
-	set_mem_limmed	0x5555,0x5555,gr25
-	set_gr_limmed	0x1111,0x1111,gr20
-	set_gr_limmed	0xffff,0xffff,gr8
-	inc_gr_immed	-4,sp
-	set_gr_immed	0,gr7
-	rst		gr8,@(sp,gr7)
-	test_mem_limmed	0x2222,0x2222,gr24
-	test_mem_limmed	0x3333,0x3333,gr27
-	test_mem_limmed	0xffff,0xffff,gr26
-	test_mem_limmed	0x5555,0x5555,gr25
-	test_gr_limmed	0xffff,0xffff,gr20
-
-	; 1 nesr active with the correct address in neear for fr
-	inc_gr_immed	-4,gr10
-	nldfi		@(sp,-4),fr20
-	test_spr_gr	neear3,gr10
-	set_mem_limmed	0x2222,0x2222,gr24
-	set_mem_limmed	0x3333,0x3333,gr27
-	set_mem_limmed	0x4444,0x4444,gr26
-	set_mem_limmed	0x5555,0x5555,gr25
-	set_fr_iimmed	0x1111,0x1111,fr20
-	set_gr_limmed	0xffff,0xffff,gr8
-	set_gr_immed	-4,gr7
-	rst		gr8,@(sp,gr7)
-	test_mem_limmed	0x2222,0x2222,gr24
-	test_mem_limmed	0x3333,0x3333,gr27
-	test_mem_limmed	0x4444,0x4444,gr26
-	test_mem_limmed	0xffff,0xffff,gr25
-	test_fr_limmed	0xffff,0xffff,fr20
-
-	pass
diff --git a/sim/testsuite/sim/frv/rstb.cgs b/sim/testsuite/sim/frv/rstb.cgs
deleted file mode 100644
index e7bab42..0000000
--- a/sim/testsuite/sim/frv/rstb.cgs
+++ /dev/null
@@ -1,72 +0,0 @@
-# frv testcase for rstb $GRk,@($GRi,$GRj)
-# mach: frv
-# as(frv): -mcpu=frv
-
-	.include "testutils.inc"
-
-	start
-
-	.global add
-add:
-	; No nesr's active
-	set_gr_gr	sp,gr21
-	set_gr_gr	gr21,gr22
-	set_gr_limmed	0x1111,0x1111,gr20
-	set_mem_limmed	0x2222,0x2222,gr21
-	set_gr_immed	0,gr7
-	set_gr_limmed	0xffff,0xffff,gr8
-	rstb		gr8,@(sp,gr7)
-	test_mem_limmed	0xff22,0x2222,sp
-	test_gr_limmed	0x1111,0x1111,gr20
-
-	; 1 nesr active with the incorrect address in neear for gr
-	inc_gr_immed	3,gr22
-	nldubi		@(sp,3),gr20
-	test_spr_gr	neear0,gr22
-	set_gr_limmed	0x1111,0x1111,gr20
-	set_mem_limmed	0x2222,0x2222,gr21
-	set_gr_limmed	0xffff,0xffff,gr8
-	inc_gr_immed	1,gr7
-	rstb		gr8,@(sp,gr7)
-	test_mem_limmed	0x22ff,0x2222,gr21
-	test_gr_limmed	0x1111,0x1111,gr20
-
-	; 1 nesr active with the incorrect address in neear for fr
-	inc_gr_immed	-1,gr22
-	nldbfi		@(sp,2),fr20
-	test_spr_gr	neear1,gr22
-	set_fr_iimmed	0x1111,0x1111,fr20
-	set_mem_limmed	0x2222,0x2222,gr21
-	set_gr_limmed	0xffff,0xffff,gr8
-	inc_gr_immed	4,sp
-	set_gr_immed	-1,gr7
-	rstb		gr8,@(sp,gr7)
-	test_mem_limmed	0x2222,0x22ff,gr21
-	test_fr_limmed	0x1111,0x1111,fr20
-
-	; 1 nesr active with the correct address in neear for gr
-	inc_gr_immed	-1,gr22
-	nldubi		@(sp,-3),gr20
-	test_spr_gr	neear2,gr22
-	set_gr_limmed	0x1111,0x1111,gr20
-	set_mem_limmed	0x2222,0x2222,gr21
-	set_gr_limmed	0xffff,0xffff,gr8
-	inc_gr_immed	-4,sp
-	set_gr_immed	1,gr7
-	rstb		gr8,@(sp,gr7)
-	test_mem_limmed	0x22ff,0x2222,gr21
-	test_gr_limmed	0x0000,0x00ff,gr20
-
-	; 1 nesr active with the correct address in neear for fr
-	inc_gr_immed	-1,gr22
-	nldbfi		@(sp,0),fr20
-	test_spr_gr	neear3,gr22
-	set_fr_iimmed	0x1111,0x1111,fr20
-	set_mem_limmed	0x2222,0x2222,gr21
-	set_gr_limmed	0xffff,0xffff,gr8
-	set_gr_immed	0,gr7
-	rstb		gr8,@(sp,gr7)
-	test_mem_limmed	0xff22,0x2222,gr21
-	test_fr_limmed	0x0000,0x00ff,fr20
-
-	pass
diff --git a/sim/testsuite/sim/frv/rstbf.cgs b/sim/testsuite/sim/frv/rstbf.cgs
deleted file mode 100644
index e35260a..0000000
--- a/sim/testsuite/sim/frv/rstbf.cgs
+++ /dev/null
@@ -1,76 +0,0 @@
-# frv testcase for rstbf $FRk,@($GRi,$GRj)
-# mach: frv
-# as(frv): -mcpu=frv
-
-	.include "testutils.inc"
-
-	start
-
-	.global add
-add:
-	; No nesr's active
-	set_gr_gr	sp,gr21
-	set_gr_gr	gr21,gr22
-	set_fr_iimmed	0x1111,0x1111,fr20
-	set_gr_limmed	0x1111,0x1111,gr20
-	set_mem_limmed	0x2222,0x2222,gr21
-	set_gr_immed	0,gr7
-	set_fr_iimmed	0xffff,0xffff,fr8
-	rstbf		fr8,@(sp,gr7)
-	test_mem_limmed	0xff22,0x2222,sp
-	test_gr_limmed	0x1111,0x1111,gr20
-	test_fr_limmed	0x1111,0x1111,fr20
-
-	; 1 nesr active with the incorrect address in neear for gr
-	inc_gr_immed	1,gr22
-	nldubi		@(sp,1),gr20
-	test_spr_gr	neear0,gr22
-	set_gr_limmed	0x1111,0x1111,gr20
-	set_fr_iimmed	0x1111,0x1111,fr20
-	set_mem_limmed	0x2222,0x2222,gr21
-	set_fr_iimmed	0xffff,0xffff,fr8
-	inc_gr_immed	2,gr7
-	rstbf		fr8,@(sp,gr7)
-	test_mem_limmed	0x2222,0xff22,gr21
-	test_gr_limmed	0x1111,0x1111,gr20
-	test_fr_limmed	0x1111,0x1111,fr20
-
-	; 1 nesr active with the incorrect address in neear for fr
-	inc_gr_immed	-1,gr22
-	nldbfi		@(sp,0),fr20
-	test_spr_gr	neear1,gr22
-	set_gr_limmed	0x1111,0x1111,gr20
-	set_fr_iimmed	0x1111,0x1111,fr20
-	set_mem_limmed	0x2222,0x2222,gr21
-	set_fr_iimmed	0xffff,0xffff,fr8
-	inc_gr_immed	4,sp
-	set_gr_immed	-1,gr7
-	rstbf		fr8,@(sp,gr7)
-	test_mem_limmed	0x2222,0x22ff,gr21
-	test_gr_limmed	0x1111,0x1111,gr20
-	test_fr_limmed	0x1111,0x1111,fr20
-
-	; 1 nesr active with the correct address in neear for gr
-	set_gr_limmed	0x1111,0x1111,gr20
-	set_fr_iimmed	0x1111,0x1111,fr20
-	set_mem_limmed	0x2222,0x2222,gr21
-	set_fr_iimmed	0xffff,0xffff,fr8
-	inc_gr_immed	-4,sp
-	set_gr_immed	1,gr7
-	rstbf		fr8,@(sp,gr7)
-	test_mem_limmed	0x22ff,0x2222,gr21
-	test_gr_limmed	0x0000,0x00ff,gr20
-	test_fr_limmed	0x1111,0x1111,fr20
-
-	; 1 nesr active with the correct address in neear for fr
-	set_gr_limmed	0x1111,0x1111,gr20
-	set_fr_iimmed	0x1111,0x1111,fr20
-	set_mem_limmed	0x2222,0x2222,gr21
-	set_fr_iimmed	0xffff,0xffff,fr8
-	set_gr_immed	0,gr7
-	rstbf		fr8,@(sp,gr7)
-	test_mem_limmed	0xff22,0x2222,gr21
-	test_gr_limmed	0x1111,0x1111,gr20
-	test_fr_limmed	0x0000,0x00ff,fr20
-
-	pass
diff --git a/sim/testsuite/sim/frv/rstd.cgs b/sim/testsuite/sim/frv/rstd.cgs
deleted file mode 100644
index bf67635..0000000
--- a/sim/testsuite/sim/frv/rstd.cgs
+++ /dev/null
@@ -1,171 +0,0 @@
-# frv testcase for rstd $GRk,@($GRi,$GRj)
-# mach: frv
-# as(frv): -mcpu=frv
-
-	.include "testutils.inc"
-
-	start
-
-	.global add
-add:
-	; No nesr's active
-	set_gr_gr	sp,gr20
-	set_mem_limmed	0x2222,0x2222,gr20
-	set_gr_gr	gr20,gr27
-	inc_gr_immed	-4,gr27
-	set_mem_limmed	0x3333,0x3333,gr27
-	set_gr_gr	gr27,gr26
-	inc_gr_immed	-4,gr26
-	set_mem_limmed	0x4444,0x4444,gr26
-	set_gr_gr	gr26,gr25
-	inc_gr_immed	-4,gr25
-	set_mem_limmed	0x5555,0x5555,gr25
-	set_gr_gr	gr25,gr24
-	inc_gr_immed	-4,gr24
-	set_mem_limmed	0x6666,0x6666,gr24
-	set_gr_gr	gr24,gr23
-	inc_gr_immed	-4,gr23
-	set_mem_limmed	0x7777,0x7777,gr23
-	set_gr_gr	gr23,gr22
-	inc_gr_immed	-4,gr22
-	set_mem_limmed	0x8888,0x8888,gr22
-	set_gr_gr	gr22,gr21
-	inc_gr_immed	-4,gr21
-	set_mem_limmed	0x9999,0x9999,gr21
-	set_gr_limmed	0x1111,0x1111,gr40
-	set_gr_limmed	0x1111,0x1111,gr41
-	inc_gr_immed	-4,sp
-	set_gr_immed	0,gr7
-	set_gr_limmed	0xeeee,0xeeee,gr8
-	set_gr_limmed	0xffff,0xffff,gr9
-	rstd		gr8,@(sp,gr7)
-	test_mem_limmed	0xffff,0xffff,gr20
-	test_mem_limmed	0xeeee,0xeeee,gr27
-	test_mem_limmed	0x4444,0x4444,gr26
-	test_mem_limmed	0x5555,0x5555,gr25
-	test_mem_limmed	0x6666,0x6666,gr24
-	test_mem_limmed	0x7777,0x7777,gr23
-	test_mem_limmed	0x8888,0x8888,gr22
-	test_mem_limmed	0x9999,0x9999,gr21
-	test_gr_limmed	0x1111,0x1111,gr40
-	test_gr_limmed	0x1111,0x1111,gr41
-
-	; 1 nesr active with the incorrect address in neear for gr
-	set_gr_gr	sp,gr10
-	nlddi		@(sp,0),gr40
-	test_spr_gr	neear0,gr10
-	set_mem_limmed	0x2222,0x2222,gr20
-	set_mem_limmed	0x3333,0x3333,gr27
-	set_mem_limmed	0x4444,0x4444,gr26
-	set_mem_limmed	0x5555,0x5555,gr25
-	set_mem_limmed	0x6666,0x6666,gr24
-	set_mem_limmed	0x7777,0x7777,gr23
-	set_mem_limmed	0x8888,0x8888,gr22
-	set_mem_limmed	0x9999,0x9999,gr21
-	set_gr_limmed	0xeeee,0xeeee,gr8
-	set_gr_limmed	0xffff,0xffff,gr9
-	set_gr_limmed	0x1111,0x1111,gr40
-	set_gr_limmed	0x1111,0x1111,gr41
-	set_gr_immed	-8,gr7
-	rstd		gr8,@(sp,gr7)
-	test_mem_limmed	0x2222,0x2222,gr20
-	test_mem_limmed	0x3333,0x3333,gr27
-	test_mem_limmed	0xffff,0xffff,gr26
-	test_mem_limmed	0xeeee,0xeeee,gr25
-	test_mem_limmed	0x6666,0x6666,gr24
-	test_mem_limmed	0x7777,0x7777,gr23
-	test_mem_limmed	0x8888,0x8888,gr22
-	test_mem_limmed	0x9999,0x9999,gr21
-	test_gr_limmed	0x1111,0x1111,gr40
-	test_gr_limmed	0x1111,0x1111,gr41
-
-	; 1 nesr active with the incorrect address in neear for fr
-	inc_gr_immed	-8,gr10
-	nlddfi		@(sp,-8),fr40
-	test_spr_gr	neear1,gr10
-	set_mem_limmed	0x2222,0x2222,gr20
-	set_mem_limmed	0x3333,0x3333,gr27
-	set_mem_limmed	0x4444,0x4444,gr26
-	set_mem_limmed	0x5555,0x5555,gr25
-	set_mem_limmed	0x6666,0x6666,gr24
-	set_mem_limmed	0x7777,0x7777,gr23
-	set_mem_limmed	0x8888,0x8888,gr22
-	set_mem_limmed	0x9999,0x9999,gr21
-	set_gr_limmed	0xeeee,0xeeee,gr8
-	set_gr_limmed	0xffff,0xffff,gr9
-	set_fr_iimmed	0x1111,0x1111,fr40
-	set_fr_iimmed	0x1111,0x1111,fr41
-	inc_gr_immed	-8,sp
-	set_gr_immed	8,gr7
-	rstd		gr8,@(sp,gr7)
-	test_mem_limmed	0xffff,0xffff,gr20
-	test_mem_limmed	0xeeee,0xeeee,gr27
-	test_mem_limmed	0x4444,0x4444,gr26
-	test_mem_limmed	0x5555,0x5555,gr25
-	test_mem_limmed	0x6666,0x6666,gr24
-	test_mem_limmed	0x7777,0x7777,gr23
-	test_mem_limmed	0x8888,0x8888,gr22
-	test_mem_limmed	0x9999,0x9999,gr21
-	test_fr_limmed	0x1111,0x1111,fr40
-	test_fr_limmed	0x1111,0x1111,fr41
-
-	; 1 nesr active with the correct address in neear for gr
-	inc_gr_immed	-8,gr10
-	nlddi		@(sp,-8),gr40
-	test_spr_gr	neear2,gr10
-	set_mem_limmed	0x2222,0x2222,gr20
-	set_mem_limmed	0x3333,0x3333,gr27
-	set_mem_limmed	0x4444,0x4444,gr26
-	set_mem_limmed	0x5555,0x5555,gr25
-	set_mem_limmed	0x6666,0x6666,gr24
-	set_mem_limmed	0x7777,0x7777,gr23
-	set_mem_limmed	0x8888,0x8888,gr22
-	set_mem_limmed	0x9999,0x9999,gr21
-	set_gr_limmed	0xeeee,0xeeee,gr8
-	set_gr_limmed	0xffff,0xffff,gr9
-	set_gr_limmed	0x1111,0x1111,gr40
-	set_gr_limmed	0x1111,0x1111,gr41
-	inc_gr_immed	-8,sp
-	set_gr_immed	0,gr7
-	rstd		gr8,@(sp,gr7)
-	test_mem_limmed	0x2222,0x2222,gr20
-	test_mem_limmed	0x3333,0x3333,gr27
-	test_mem_limmed	0x4444,0x4444,gr26
-	test_mem_limmed	0x5555,0x5555,gr25
-	test_mem_limmed	0xffff,0xffff,gr24
-	test_mem_limmed	0xeeee,0xeeee,gr23
-	test_mem_limmed	0x8888,0x8888,gr22
-	test_mem_limmed	0x9999,0x9999,gr21
-	test_gr_limmed	0xffff,0xffff,gr41
-	test_gr_limmed	0xeeee,0xeeee,gr40
-
-	; 1 nesr active with the correct address in neear for fr
-	inc_gr_immed	-8,gr10
-	nlddfi		@(sp,-8),fr40
-	test_spr_gr	neear3,gr10
-	set_mem_limmed	0x2222,0x2222,gr20
-	set_mem_limmed	0x3333,0x3333,gr27
-	set_mem_limmed	0x4444,0x4444,gr26
-	set_mem_limmed	0x5555,0x5555,gr25
-	set_mem_limmed	0x6666,0x6666,gr24
-	set_mem_limmed	0x7777,0x7777,gr23
-	set_mem_limmed	0x8888,0x8888,gr22
-	set_mem_limmed	0x9999,0x9999,gr21
-	set_gr_limmed	0xeeee,0xeeee,gr8
-	set_gr_limmed	0xffff,0xffff,gr9
-	set_fr_iimmed	0x1111,0x1111,fr40
-	set_fr_iimmed	0x1111,0x1111,fr41
-	set_gr_immed	-8,gr7
-	rstd		gr8,@(sp,gr7)
-	test_mem_limmed	0x2222,0x2222,gr20
-	test_mem_limmed	0x3333,0x3333,gr27
-	test_mem_limmed	0x4444,0x4444,gr26
-	test_mem_limmed	0x5555,0x5555,gr25
-	test_mem_limmed	0x6666,0x6666,gr24
-	test_mem_limmed	0x7777,0x7777,gr23
-	test_mem_limmed	0xffff,0xffff,gr22
-	test_mem_limmed	0xeeee,0xeeee,gr21
-	test_fr_limmed	0xffff,0xffff,fr41
-	test_fr_limmed	0xeeee,0xeeee,fr40
-
-	pass
diff --git a/sim/testsuite/sim/frv/rstdf.cgs b/sim/testsuite/sim/frv/rstdf.cgs
deleted file mode 100644
index 9d0d841..0000000
--- a/sim/testsuite/sim/frv/rstdf.cgs
+++ /dev/null
@@ -1,186 +0,0 @@
-# frv testcase for rstdf $FRk,@($GRi,$GRj)
-# mach: frv
-# as(frv): -mcpu=frv
-
-	.include "testutils.inc"
-
-	start
-
-	.global add
-add:
-	; No nesr's active
-	set_gr_gr	sp,gr20
-	set_mem_limmed	0x2222,0x2222,gr20
-	set_gr_gr	gr20,gr27
-	inc_gr_immed	-4,gr27
-	set_mem_limmed	0x3333,0x3333,gr27
-	set_gr_gr	gr27,gr26
-	inc_gr_immed	-4,gr26
-	set_mem_limmed	0x4444,0x4444,gr26
-	set_gr_gr	gr26,gr25
-	inc_gr_immed	-4,gr25
-	set_mem_limmed	0x5555,0x5555,gr25
-	set_gr_gr	gr25,gr24
-	inc_gr_immed	-4,gr24
-	set_mem_limmed	0x6666,0x6666,gr24
-	set_gr_gr	gr24,gr23
-	inc_gr_immed	-4,gr23
-	set_mem_limmed	0x7777,0x7777,gr23
-	set_gr_gr	gr23,gr22
-	inc_gr_immed	-4,gr22
-	set_mem_limmed	0x8888,0x8888,gr22
-	set_gr_gr	gr22,gr21
-	inc_gr_immed	-4,gr21
-	set_mem_limmed	0x9999,0x9999,gr21
-	set_gr_limmed	0x1111,0x1111,gr40
-	set_gr_limmed	0x1111,0x1111,gr41
-	set_fr_iimmed	0x1111,0x1111,fr40
-	set_fr_iimmed	0x1111,0x1111,fr41
-	inc_gr_immed	-4,sp
-	set_gr_immed	0,gr7
-	set_fr_iimmed	0xeeee,0xeeee,fr8
-	set_fr_iimmed	0xffff,0xffff,fr9
-	rstdf		fr8,@(sp,gr7)
-	test_mem_limmed	0xffff,0xffff,gr20
-	test_mem_limmed	0xeeee,0xeeee,gr27
-	test_mem_limmed	0x4444,0x4444,gr26
-	test_mem_limmed	0x5555,0x5555,gr25
-	test_mem_limmed	0x6666,0x6666,gr24
-	test_mem_limmed	0x7777,0x7777,gr23
-	test_mem_limmed	0x8888,0x8888,gr22
-	test_mem_limmed	0x9999,0x9999,gr21
-	test_gr_limmed	0x1111,0x1111,gr40
-	test_gr_limmed	0x1111,0x1111,gr41
-	test_fr_limmed	0x1111,0x1111,fr40
-	test_fr_limmed	0x1111,0x1111,fr41
-
-	; 1 nesr active with the incorrect address in neear for gr
-	set_gr_gr	sp,gr10
-	inc_gr_immed	-16,gr10
-	nlddi		@(sp,-16),gr40
-	test_spr_gr	neear0,gr10
-	set_mem_limmed	0x2222,0x2222,gr20
-	set_mem_limmed	0x3333,0x3333,gr27
-	set_mem_limmed	0x4444,0x4444,gr26
-	set_mem_limmed	0x5555,0x5555,gr25
-	set_mem_limmed	0x6666,0x6666,gr24
-	set_mem_limmed	0x7777,0x7777,gr23
-	set_mem_limmed	0x8888,0x8888,gr22
-	set_mem_limmed	0x9999,0x9999,gr21
-	set_fr_iimmed	0xeeee,0xeeee,fr8
-	set_fr_iimmed	0xffff,0xffff,fr9
-	set_gr_limmed	0x1111,0x1111,gr40
-	set_gr_limmed	0x1111,0x1111,gr41
-	set_fr_iimmed	0x1111,0x1111,fr40
-	set_fr_iimmed	0x1111,0x1111,fr41
-	set_gr_immed	-8,gr7
-	rstdf		fr8,@(sp,gr7)
-	test_mem_limmed	0x2222,0x2222,gr20
-	test_mem_limmed	0x3333,0x3333,gr27
-	test_mem_limmed	0xffff,0xffff,gr26
-	test_mem_limmed	0xeeee,0xeeee,gr25
-	test_mem_limmed	0x6666,0x6666,gr24
-	test_mem_limmed	0x7777,0x7777,gr23
-	test_mem_limmed	0x8888,0x8888,gr22
-	test_mem_limmed	0x9999,0x9999,gr21
-	test_gr_limmed	0x1111,0x1111,gr40
-	test_gr_limmed	0x1111,0x1111,gr41
-	test_fr_limmed	0x1111,0x1111,fr40
-	test_fr_limmed	0x1111,0x1111,fr41
-
-	; 1 nesr active with the incorrect address in neear for fr
-	inc_gr_immed	-8,gr10
-	nlddfi		@(sp,-24),fr40
-	test_spr_gr	neear1,gr10
-	set_mem_limmed	0x2222,0x2222,gr20
-	set_mem_limmed	0x3333,0x3333,gr27
-	set_mem_limmed	0x4444,0x4444,gr26
-	set_mem_limmed	0x5555,0x5555,gr25
-	set_mem_limmed	0x6666,0x6666,gr24
-	set_mem_limmed	0x7777,0x7777,gr23
-	set_mem_limmed	0x8888,0x8888,gr22
-	set_mem_limmed	0x9999,0x9999,gr21
-	set_fr_iimmed	0xeeee,0xeeee,fr8
-	set_fr_iimmed	0xffff,0xffff,fr9
-	set_gr_limmed	0x1111,0x1111,gr40
-	set_gr_limmed	0x1111,0x1111,gr41
-	set_fr_iimmed	0x1111,0x1111,fr40
-	set_fr_iimmed	0x1111,0x1111,fr41
-	inc_gr_immed	-8,sp
-	set_gr_immed	8,gr7
-	rstdf		fr8,@(sp,gr7)
-	test_mem_limmed	0xffff,0xffff,gr20
-	test_mem_limmed	0xeeee,0xeeee,gr27
-	test_mem_limmed	0x4444,0x4444,gr26
-	test_mem_limmed	0x5555,0x5555,gr25
-	test_mem_limmed	0x6666,0x6666,gr24
-	test_mem_limmed	0x7777,0x7777,gr23
-	test_mem_limmed	0x8888,0x8888,gr22
-	test_mem_limmed	0x9999,0x9999,gr21
-	test_gr_limmed	0x1111,0x1111,gr40
-	test_gr_limmed	0x1111,0x1111,gr41
-	test_fr_limmed	0x1111,0x1111,fr40
-	test_fr_limmed	0x1111,0x1111,fr41
-
-	; 1 nesr active with the correct address in neear for gr
-	set_mem_limmed	0x2222,0x2222,gr20
-	set_mem_limmed	0x3333,0x3333,gr27
-	set_mem_limmed	0x4444,0x4444,gr26
-	set_mem_limmed	0x5555,0x5555,gr25
-	set_mem_limmed	0x6666,0x6666,gr24
-	set_mem_limmed	0x7777,0x7777,gr23
-	set_mem_limmed	0x8888,0x8888,gr22
-	set_mem_limmed	0x9999,0x9999,gr21
-	set_fr_iimmed	0xeeee,0xeeee,fr8
-	set_fr_iimmed	0xffff,0xffff,fr9
-	set_gr_limmed	0x1111,0x1111,gr40
-	set_gr_limmed	0x1111,0x1111,gr41
-	set_fr_iimmed	0x1111,0x1111,fr40
-	set_fr_iimmed	0x1111,0x1111,fr41
-	inc_gr_immed	-8,sp
-	set_gr_immed	0,gr7
-	rstdf		fr8,@(sp,gr7)
-	test_mem_limmed	0x2222,0x2222,gr20
-	test_mem_limmed	0x3333,0x3333,gr27
-	test_mem_limmed	0x4444,0x4444,gr26
-	test_mem_limmed	0x5555,0x5555,gr25
-	test_mem_limmed	0xffff,0xffff,gr24
-	test_mem_limmed	0xeeee,0xeeee,gr23
-	test_mem_limmed	0x8888,0x8888,gr22
-	test_mem_limmed	0x9999,0x9999,gr21
-	test_gr_limmed	0xffff,0xffff,gr41
-	test_gr_limmed	0xeeee,0xeeee,gr40
-	test_fr_limmed	0x1111,0x1111,fr41
-	test_fr_limmed	0x1111,0x1111,fr40
-
-	; 1 nesr active with the correct address in neear for fr
-	set_mem_limmed	0x2222,0x2222,gr20
-	set_mem_limmed	0x3333,0x3333,gr27
-	set_mem_limmed	0x4444,0x4444,gr26
-	set_mem_limmed	0x5555,0x5555,gr25
-	set_mem_limmed	0x6666,0x6666,gr24
-	set_mem_limmed	0x7777,0x7777,gr23
-	set_mem_limmed	0x8888,0x8888,gr22
-	set_mem_limmed	0x9999,0x9999,gr21
-	set_fr_iimmed	0xeeee,0xeeee,fr8
-	set_fr_iimmed	0xffff,0xffff,fr9
-	set_gr_limmed	0x1111,0x1111,gr40
-	set_gr_limmed	0x1111,0x1111,gr41
-	set_fr_iimmed	0x1111,0x1111,fr40
-	set_fr_iimmed	0x1111,0x1111,fr41
-	set_gr_immed	-8,gr7
-	rstdf		fr8,@(sp,gr7)
-	test_mem_limmed	0x2222,0x2222,gr20
-	test_mem_limmed	0x3333,0x3333,gr27
-	test_mem_limmed	0x4444,0x4444,gr26
-	test_mem_limmed	0x5555,0x5555,gr25
-	test_mem_limmed	0x6666,0x6666,gr24
-	test_mem_limmed	0x7777,0x7777,gr23
-	test_mem_limmed	0xffff,0xffff,gr22
-	test_mem_limmed	0xeeee,0xeeee,gr21
-	test_gr_limmed	0x1111,0x1111,gr41
-	test_gr_limmed	0x1111,0x1111,gr40
-	test_fr_limmed	0xffff,0xffff,fr41
-	test_fr_limmed	0xeeee,0xeeee,fr40
-
-	pass
diff --git a/sim/testsuite/sim/frv/rstf.cgs b/sim/testsuite/sim/frv/rstf.cgs
deleted file mode 100644
index 17a123a..0000000
--- a/sim/testsuite/sim/frv/rstf.cgs
+++ /dev/null
@@ -1,112 +0,0 @@
-# frv testcase for rstf $FRk,@($GRi,$GRj)
-# mach: frv
-# as(frv): -mcpu=frv
-
-	.include "testutils.inc"
-
-	start
-
-	.global add
-add:
-	; No nesr's active
-	set_gr_gr	sp,gr10
-	set_gr_gr	sp,gr24
-	set_mem_limmed	0x2222,0x2222,gr24
-	set_gr_gr	gr24,gr27
-	inc_gr_immed	-4,gr27
-	set_mem_limmed	0x3333,0x3333,gr27
-	set_gr_gr	gr27,gr26
-	inc_gr_immed	-4,gr26
-	set_mem_limmed	0x4444,0x4444,gr26
-	set_gr_gr	gr26,gr25
-	inc_gr_immed	-4,gr25
-	set_mem_limmed	0x5555,0x5555,gr25
-	set_gr_limmed	0x1111,0x1111,gr20
-	set_fr_iimmed	0x1111,0x1111,fr20
-	set_gr_immed	0,gr7
-	set_fr_iimmed	0xffff,0xffff,fr8
-	rstf		fr8,@(sp,gr7)
-	test_mem_limmed	0xffff,0xffff,gr24
-	test_mem_limmed	0x3333,0x3333,gr27
-	test_mem_limmed	0x4444,0x4444,gr26
-	test_mem_limmed	0x5555,0x5555,gr25
-	test_gr_limmed	0x1111,0x1111,gr20
-	test_fr_limmed	0x1111,0x1111,fr20
-
-	; 1 nesr active with the incorrect address in neear for gr
-	inc_gr_immed	-8,gr10
-	nldi		@(sp,-8),gr20
-	test_spr_gr	neear0,gr10
-	set_mem_limmed	0x2222,0x2222,gr24
-	set_mem_limmed	0x3333,0x3333,gr27
-	set_mem_limmed	0x4444,0x4444,gr26
-	set_mem_limmed	0x5555,0x5555,gr25
-	set_gr_limmed	0x1111,0x1111,gr20
-	set_fr_iimmed	0x1111,0x1111,fr20
-	set_fr_iimmed	0xffff,0xffff,fr8
-	set_gr_immed	-4,gr7
-	rstf		fr8,@(sp,gr7)
-	test_mem_limmed	0x2222,0x2222,gr24
-	test_mem_limmed	0xffff,0xffff,gr27
-	test_mem_limmed	0x4444,0x4444,gr26
-	test_mem_limmed	0x5555,0x5555,gr25
-	test_gr_limmed	0x1111,0x1111,gr20
-	test_fr_limmed	0x1111,0x1111,fr20
-
-	; 1 nesr active with the incorrect address in neear for fr
-	inc_gr_immed	-4,gr10
-	nldfi		@(sp,-12),fr20
-	test_spr_gr	neear1,gr10
-	set_mem_limmed	0x2222,0x2222,gr24
-	set_mem_limmed	0x3333,0x3333,gr27
-	set_mem_limmed	0x4444,0x4444,gr26
-	set_mem_limmed	0x5555,0x5555,gr25
-	set_gr_limmed	0x1111,0x1111,gr20
-	set_fr_iimmed	0x1111,0x1111,fr20
-	set_fr_iimmed	0xffff,0xffff,fr8
-	inc_gr_immed	-4,sp
-	set_gr_immed	4,gr7
-	rstf		fr8,@(sp,gr7)
-	test_mem_limmed	0xffff,0xffff,gr24
-	test_mem_limmed	0x3333,0x3333,gr27
-	test_mem_limmed	0x4444,0x4444,gr26
-	test_mem_limmed	0x5555,0x5555,gr25
-	test_gr_limmed	0x1111,0x1111,gr20
-	test_fr_limmed	0x1111,0x1111,fr20
-
-	; 1 nesr active with the correct address in neear for gr
-	set_mem_limmed	0x2222,0x2222,gr24
-	set_mem_limmed	0x3333,0x3333,gr27
-	set_mem_limmed	0x4444,0x4444,gr26
-	set_mem_limmed	0x5555,0x5555,gr25
-	set_gr_limmed	0x1111,0x1111,gr20
-	set_fr_iimmed	0x1111,0x1111,fr20
-	set_fr_iimmed	0xffff,0xffff,fr8
-	inc_gr_immed	-4,sp
-	set_gr_immed	0,gr7
-	rstf		fr8,@(sp,gr7)
-	test_mem_limmed	0x2222,0x2222,gr24
-	test_mem_limmed	0x3333,0x3333,gr27
-	test_mem_limmed	0xffff,0xffff,gr26
-	test_mem_limmed	0x5555,0x5555,gr25
-	test_gr_limmed	0xffff,0xffff,gr20
-	test_fr_limmed	0x1111,0x1111,fr20
-
-	; 1 nesr active with the correct address in neear for fr
-	set_mem_limmed	0x2222,0x2222,gr24
-	set_mem_limmed	0x3333,0x3333,gr27
-	set_mem_limmed	0x4444,0x4444,gr26
-	set_mem_limmed	0x5555,0x5555,gr25
-	set_gr_limmed	0x1111,0x1111,gr20
-	set_fr_iimmed	0x1111,0x1111,fr20
-	set_fr_iimmed	0xffff,0xffff,fr8
-	set_gr_immed	-4,gr7
-	rstf		fr8,@(sp,gr7)
-	test_mem_limmed	0x2222,0x2222,gr24
-	test_mem_limmed	0x3333,0x3333,gr27
-	test_mem_limmed	0x4444,0x4444,gr26
-	test_mem_limmed	0xffff,0xffff,gr25
-	test_gr_limmed	0x1111,0x1111,gr20
-	test_fr_limmed	0xffff,0xffff,fr20
-
-	pass
diff --git a/sim/testsuite/sim/frv/rsth.cgs b/sim/testsuite/sim/frv/rsth.cgs
deleted file mode 100644
index a2b283e..0000000
--- a/sim/testsuite/sim/frv/rsth.cgs
+++ /dev/null
@@ -1,83 +0,0 @@
-# frv testcase for rsth $GRk,@($GRi,$GRj)
-# mach: frv
-# as(frv): -mcpu=frv
-
-	.include "testutils.inc"
-
-	start
-
-	.global add
-add:
-	; No nesr's active
-	set_gr_gr	sp,gr22
-	set_mem_limmed	0x2222,0x2222,gr22
-	set_gr_gr	gr22,gr21
-	inc_gr_immed	-4,gr21
-	set_mem_limmed	0x3333,0x3333,gr21
-	set_gr_gr	gr22,gr23
-	set_gr_limmed	0x1111,0x1111,gr20
-	set_gr_immed	0,gr7
-	set_gr_limmed	0xffff,0xffff,gr8
-	rsth		gr8,@(sp,gr7)
-	test_mem_limmed	0xffff,0x2222,gr22
-	test_mem_limmed	0x3333,0x3333,gr21
-	test_gr_limmed	0x1111,0x1111,gr20
-
-	; 1 nesr active with the incorrect address in neear for gr
-	nlduhi		@(sp,0),gr20
-	test_spr_gr	neear0,gr23
-	set_mem_limmed	0x2222,0x2222,gr22
-	set_mem_limmed	0x3333,0x3333,gr21
-	set_gr_limmed	0x1111,0x1111,gr20
-	set_gr_limmed	0xffff,0xffff,gr8
-	set_gr_immed	2,gr7
-	rsth		gr8,@(sp,gr7)
-	test_mem_limmed	0x2222,0xffff,gr22
-	test_mem_limmed	0x3333,0x3333,gr21
-	test_gr_limmed	0x1111,0x1111,gr20
-
-	; 1 nesr active with the incorrect address in neear for fr
-	inc_gr_immed	2,gr23
-	nldhfi		@(sp,2),fr20
-	test_spr_gr	neear1,gr23
-	set_mem_limmed	0x2222,0x2222,gr22
-	set_mem_limmed	0x3333,0x3333,gr21
-	set_fr_iimmed	0x1111,0x1111,fr20
-	set_gr_limmed	0xffff,0xffff,gr8
-	inc_gr_immed	4,sp
-	set_gr_immed	-4,gr7
-	rsth		gr8,@(sp,gr7)
-	test_mem_limmed	0xffff,0x2222,gr22
-	test_mem_limmed	0x3333,0x3333,gr21
-	test_fr_limmed	0x1111,0x1111,fr20
-
-	; 1 nesr active with the correct address in neear for gr
-	inc_gr_immed	-4,gr23
-	nlduhi		@(sp,-6),gr20
-	test_spr_gr	neear2,gr23
-	set_mem_limmed	0x2222,0x2222,gr22
-	set_mem_limmed	0x3333,0x3333,gr21
-	set_gr_limmed	0x1111,0x1111,gr20
-	set_gr_limmed	0xffff,0xffff,gr8
-	inc_gr_immed	-4,sp
-	set_gr_immed	-2,gr7
-	rsth		gr8,@(sp,gr7)
-	test_mem_limmed	0x2222,0x2222,gr22
-	test_mem_limmed	0x3333,0xffff,gr21
-	test_gr_limmed	0x0000,0xffff,gr20
-
-	; 1 nesr active with the correct address in neear for fr
-	inc_gr_immed	-2,gr23
-	nldhfi		@(sp,-4),fr20
-	test_spr_gr	neear3,gr23
-	set_mem_limmed	0x2222,0x2222,gr22
-	set_mem_limmed	0x3333,0x3333,gr21
-	set_fr_iimmed	0x1111,0x1111,fr20
-	set_gr_limmed	0xffff,0xffff,gr8
-	set_gr_immed	-4,gr7
-	rsth		gr8,@(sp,gr7)
-	test_mem_limmed	0x2222,0x2222,gr22
-	test_mem_limmed	0xffff,0x3333,gr21
-	test_fr_limmed	0x0000,0xffff,fr20
-
-	pass
diff --git a/sim/testsuite/sim/frv/rsthf.cgs b/sim/testsuite/sim/frv/rsthf.cgs
deleted file mode 100644
index 06adb97..0000000
--- a/sim/testsuite/sim/frv/rsthf.cgs
+++ /dev/null
@@ -1,87 +0,0 @@
-# frv testcase for rsthf $FRk,@($GRi,$GRj)
-# mach: frv
-# as(frv): -mcpu=frv
-
-	.include "testutils.inc"
-
-	start
-
-	.global add
-add:
-	; No nesr's active
-	set_gr_gr	sp,gr22
-	set_mem_limmed	0x2222,0x2222,gr22
-	set_gr_gr	gr22,gr21
-	inc_gr_immed	-4,gr21
-	set_mem_limmed	0x3333,0x3333,gr21
-	set_gr_gr	gr22,gr23
-	set_gr_limmed	0x1111,0x1111,gr20
-	set_fr_iimmed	0x1111,0x1111,fr20
-	set_gr_immed	0,gr7
-	set_fr_iimmed	0xffff,0xffff,fr8
-	rsthf		fr8,@(sp,gr7)
-	test_mem_limmed	0xffff,0x2222,gr22
-	test_mem_limmed	0x3333,0x3333,gr21
-	test_gr_limmed	0x1111,0x1111,gr20
-	test_fr_limmed	0x1111,0x1111,fr20
-
-	; 1 nesr active with the incorrect address in neear for gr
-	inc_gr_immed	-2,gr23
-	nlduhi		@(sp,-2),gr20
-	test_spr_gr	neear0,gr23
-	set_mem_limmed	0x2222,0x2222,gr22
-	set_mem_limmed	0x3333,0x3333,gr21
-	set_gr_limmed	0x1111,0x1111,gr20
-	set_fr_iimmed	0xffff,0xffff,fr8
-	set_gr_immed	2,gr7
-	rsthf		fr8,@(sp,gr7)
-	test_mem_limmed	0x2222,0xffff,gr22
-	test_mem_limmed	0x3333,0x3333,gr21
-	test_gr_limmed	0x1111,0x1111,gr20
-	test_fr_limmed	0x1111,0x1111,fr20
-
-	; 1 nesr active with the incorrect address in neear for fr
-	inc_gr_immed	-2,gr23
-	nldhfi		@(sp,-4),fr20
-	test_spr_gr	neear1,gr23
-	set_mem_limmed	0x2222,0x2222,gr22
-	set_mem_limmed	0x3333,0x3333,gr21
-	set_gr_limmed	0x1111,0x1111,gr20
-	set_fr_iimmed	0x1111,0x1111,fr20
-	set_fr_iimmed	0xffff,0xffff,fr8
-	inc_gr_immed	4,sp
-	set_gr_immed	-4,gr7
-	rsthf		fr8,@(sp,gr7)
-	test_mem_limmed	0xffff,0x2222,gr22
-	test_mem_limmed	0x3333,0x3333,gr21
-	test_gr_limmed	0x1111,0x1111,gr20
-	test_fr_limmed	0x1111,0x1111,fr20
-
-	; 1 nesr active with the correct address in neear for gr
-	set_mem_limmed	0x2222,0x2222,gr22
-	set_mem_limmed	0x3333,0x3333,gr21
-	set_gr_limmed	0x1111,0x1111,gr20
-	set_fr_iimmed	0x1111,0x1111,fr20
-	set_fr_iimmed	0xffff,0xffff,fr8
-	inc_gr_immed	-4,sp
-	set_gr_immed	-2,gr7
-	rsthf		fr8,@(sp,gr7)
-	test_mem_limmed	0x2222,0x2222,gr22
-	test_mem_limmed	0x3333,0xffff,gr21
-	test_gr_limmed	0x0000,0xffff,gr20
-	test_fr_limmed	0x1111,0x1111,fr20
-
-	; 1 nesr active with the correct address in neear for fr
-	set_mem_limmed	0x2222,0x2222,gr22
-	set_mem_limmed	0x3333,0x3333,gr21
-	set_gr_limmed	0x1111,0x1111,gr20
-	set_fr_iimmed	0x1111,0x1111,fr20
-	set_fr_iimmed	0xffff,0xffff,fr8
-	set_gr_immed	-4,gr7
-	rsthf		fr8,@(sp,gr7)
-	test_mem_limmed	0x2222,0x2222,gr22
-	test_mem_limmed	0xffff,0x3333,gr21
-	test_gr_limmed	0x1111,0x1111,gr20
-	test_fr_limmed	0x0000,0xffff,fr20
-
-	pass
diff --git a/sim/testsuite/sim/frv/rstq.cgs b/sim/testsuite/sim/frv/rstq.cgs
deleted file mode 100644
index 190c954..0000000
--- a/sim/testsuite/sim/frv/rstq.cgs
+++ /dev/null
@@ -1,297 +0,0 @@
-# frv testcase for rstq $GRk,@($GRi,$GRj)
-# mach: frv
-# as(frv): -mcpu=frv
-
-	.include "testutils.inc"
-
-	start
-
-	.global add
-add:
-	; No nesr's active
-	set_gr_gr	sp,gr6
-	set_mem_limmed	0x2222,0x2222,gr6
-	set_gr_gr	gr6,gr27
-	inc_gr_immed	-4,gr27
-	set_mem_limmed	0x3333,0x3333,gr27
-	set_gr_gr	gr27,gr26
-	inc_gr_immed	-4,gr26
-	set_mem_limmed	0x4444,0x4444,gr26
-	set_gr_gr	gr26,gr25
-	inc_gr_immed	-4,gr25
-	set_mem_limmed	0x5555,0x5555,gr25
-	set_gr_gr	gr25,gr24
-	inc_gr_immed	-4,gr24
-	set_mem_limmed	0x6666,0x6666,gr24
-	set_gr_gr	gr24,gr23
-	inc_gr_immed	-4,gr23
-	set_mem_limmed	0x7777,0x7777,gr23
-	set_gr_gr	gr23,gr22
-	inc_gr_immed	-4,gr22
-	set_mem_limmed	0x8888,0x8888,gr22
-	set_gr_gr	gr22,gr21
-	inc_gr_immed	-4,gr21
-	set_mem_limmed	0x9999,0x9999,gr21
-	set_gr_gr	gr21,gr20
-	inc_gr_immed	-4,gr20
-	set_mem_limmed	0xaaaa,0xaaaa,gr20
-	set_gr_gr	gr20,gr19
-	inc_gr_immed	-4,gr19
-	set_mem_limmed	0xbbbb,0xbbbb,gr19
-	set_gr_gr	gr19,gr18
-	inc_gr_immed	-4,gr18
-	set_mem_limmed	0xcccc,0xcccc,gr18
-	set_gr_gr	gr18,gr17
-	inc_gr_immed	-4,gr17
-	set_mem_limmed	0xdddd,0xdddd,gr17
-	set_gr_gr	gr17,gr16
-	inc_gr_immed	-4,gr16
-	set_mem_limmed	0xeeee,0xeeee,gr16
-	set_gr_gr	gr16,gr15
-	inc_gr_immed	-4,gr15
-	set_mem_limmed	0xf0f0,0xf0f0,gr15
-	set_gr_gr	gr15,gr14
-	inc_gr_immed	-4,gr14
-	set_mem_limmed	0xf1f1,0xf1f1,gr14
-	set_gr_gr	gr14,gr13
-	inc_gr_immed	-4,gr13
-	set_mem_limmed	0xf2f2,0xf2f2,gr13
-	set_gr_limmed	0x1111,0x1111,gr40
-	set_gr_limmed	0x1111,0x1111,gr41
-	set_gr_limmed	0x1111,0x1111,gr42
-	set_gr_limmed	0x1111,0x1111,gr43
-	inc_gr_immed	-12,sp
-	set_gr_immed	0,gr7
-	set_gr_limmed	0xeeee,0xeeee,gr8
-	set_gr_limmed	0xffff,0xffff,gr9
-	set_gr_limmed	0xcccc,0xcccc,gr10
-	set_gr_limmed	0xdddd,0xdddd,gr11
-	rstq		gr8,@(sp,gr7)
-	test_mem_limmed	0xdddd,0xdddd,gr6
-	test_mem_limmed	0xcccc,0xcccc,gr27
-	test_mem_limmed	0xffff,0xffff,gr26
-	test_mem_limmed	0xeeee,0xeeee,gr25
-	test_mem_limmed	0x6666,0x6666,gr24
-	test_mem_limmed	0x7777,0x7777,gr23
-	test_mem_limmed	0x8888,0x8888,gr22
-	test_mem_limmed	0x9999,0x9999,gr21
-	test_mem_limmed	0xaaaa,0xaaaa,gr20
-	test_mem_limmed	0xbbbb,0xbbbb,gr19
-	test_mem_limmed	0xcccc,0xcccc,gr18
-	test_mem_limmed	0xdddd,0xdddd,gr17
-	test_mem_limmed	0xeeee,0xeeee,gr16
-	test_mem_limmed	0xf0f0,0xf0f0,gr15
-	test_mem_limmed	0xf1f1,0xf1f1,gr14
-	test_mem_limmed	0xf2f2,0xf2f2,gr13
-	test_gr_limmed	0x1111,0x1111,gr40
-	test_gr_limmed	0x1111,0x1111,gr41
-	test_gr_limmed	0x1111,0x1111,gr42
-	test_gr_limmed	0x1111,0x1111,gr43
-
-	; 1 nesr active with the incorrect address in neear for gr
-	set_gr_gr	sp,gr12
-	nldq		@(sp,gr0),gr40
-	test_spr_gr	neear0,gr12
-	set_mem_limmed	0x2222,0x2222,gr6
-	set_mem_limmed	0x3333,0x3333,gr27
-	set_mem_limmed	0x4444,0x4444,gr26
-	set_mem_limmed	0x5555,0x5555,gr25
-	set_mem_limmed	0x6666,0x6666,gr24
-	set_mem_limmed	0x7777,0x7777,gr23
-	set_mem_limmed	0x8888,0x8888,gr22
-	set_mem_limmed	0x9999,0x9999,gr21
-	set_mem_limmed	0xaaaa,0xaaaa,gr20
-	set_mem_limmed	0xbbbb,0xbbbb,gr19
-	set_mem_limmed	0xcccc,0xcccc,gr18
-	set_mem_limmed	0xdddd,0xdddd,gr17
-	set_mem_limmed	0xeeee,0xeeee,gr16
-	set_mem_limmed	0xf0f0,0xf0f0,gr15
-	set_mem_limmed	0xf1f1,0xf1f1,gr14
-	set_mem_limmed	0xf2f2,0xf2f2,gr13
-	set_gr_limmed	0xeeee,0xeeee,gr8
-	set_gr_limmed	0xffff,0xffff,gr9
-	set_gr_limmed	0xcccc,0xcccc,gr10
-	set_gr_limmed	0xdddd,0xdddd,gr11
-	set_gr_limmed	0x1111,0x1111,gr40
-	set_gr_limmed	0x1111,0x1111,gr41
-	set_gr_limmed	0x1111,0x1111,gr42
-	set_gr_limmed	0x1111,0x1111,gr43
-	set_gr_immed	-16,gr7
-	rstq		gr8,@(sp,gr7)
-	test_mem_limmed	0x2222,0x2222,gr6
-	test_mem_limmed	0x3333,0x3333,gr27
-	test_mem_limmed	0x4444,0x4444,gr26
-	test_mem_limmed	0x5555,0x5555,gr25
-	test_mem_limmed	0xdddd,0xdddd,gr24
-	test_mem_limmed	0xcccc,0xcccc,gr23
-	test_mem_limmed	0xffff,0xffff,gr22
-	test_mem_limmed	0xeeee,0xeeee,gr21
-	test_mem_limmed	0xaaaa,0xaaaa,gr20
-	test_mem_limmed	0xbbbb,0xbbbb,gr19
-	test_mem_limmed	0xcccc,0xcccc,gr18
-	test_mem_limmed	0xdddd,0xdddd,gr17
-	test_mem_limmed	0xeeee,0xeeee,gr16
-	test_mem_limmed	0xf0f0,0xf0f0,gr15
-	test_mem_limmed	0xf1f1,0xf1f1,gr14
-	test_mem_limmed	0xf2f2,0xf2f2,gr13
-	test_gr_limmed	0x1111,0x1111,gr40
-	test_gr_limmed	0x1111,0x1111,gr41
-	test_gr_limmed	0x1111,0x1111,gr42
-	test_gr_limmed	0x1111,0x1111,gr43
-
-	; 1 nesr active with the incorrect address in neear for fr
-	inc_gr_immed	-16,gr12
-	nlddfi		@(sp,-16),fr40
-	test_spr_gr	neear1,gr12
-	set_mem_limmed	0x2222,0x2222,gr6
-	set_mem_limmed	0x3333,0x3333,gr27
-	set_mem_limmed	0x4444,0x4444,gr26
-	set_mem_limmed	0x5555,0x5555,gr25
-	set_mem_limmed	0x6666,0x6666,gr24
-	set_mem_limmed	0x7777,0x7777,gr23
-	set_mem_limmed	0x8888,0x8888,gr22
-	set_mem_limmed	0x9999,0x9999,gr21
-	set_mem_limmed	0xaaaa,0xaaaa,gr20
-	set_mem_limmed	0xbbbb,0xbbbb,gr19
-	set_mem_limmed	0xcccc,0xcccc,gr18
-	set_mem_limmed	0xdddd,0xdddd,gr17
-	set_mem_limmed	0xeeee,0xeeee,gr16
-	set_mem_limmed	0xf0f0,0xf0f0,gr15
-	set_mem_limmed	0xf1f1,0xf1f1,gr14
-	set_mem_limmed	0xf2f2,0xf2f2,gr13
-	set_gr_limmed	0xeeee,0xeeee,gr8
-	set_gr_limmed	0xffff,0xffff,gr9
-	set_gr_limmed	0xcccc,0xcccc,gr10
-	set_gr_limmed	0xdddd,0xdddd,gr11
-	set_fr_iimmed	0x1111,0x1111,fr40
-	set_fr_iimmed	0x1111,0x1111,fr41
-	set_fr_iimmed	0x1111,0x1111,fr42
-	set_fr_iimmed	0x1111,0x1111,fr43
-	inc_gr_immed	-16,sp
-	set_gr_immed	16,gr7
-	rstq		gr8,@(sp,gr7)
-	test_mem_limmed	0xdddd,0xdddd,gr6
-	test_mem_limmed	0xcccc,0xcccc,gr27
-	test_mem_limmed	0xffff,0xffff,gr26
-	test_mem_limmed	0xeeee,0xeeee,gr25
-	test_mem_limmed	0x6666,0x6666,gr24
-	test_mem_limmed	0x7777,0x7777,gr23
-	test_mem_limmed	0x8888,0x8888,gr22
-	test_mem_limmed	0x9999,0x9999,gr21
-	test_mem_limmed	0xaaaa,0xaaaa,gr20
-	test_mem_limmed	0xbbbb,0xbbbb,gr19
-	test_mem_limmed	0xcccc,0xcccc,gr18
-	test_mem_limmed	0xdddd,0xdddd,gr17
-	test_mem_limmed	0xeeee,0xeeee,gr16
-	test_mem_limmed	0xf0f0,0xf0f0,gr15
-	test_mem_limmed	0xf1f1,0xf1f1,gr14
-	test_mem_limmed	0xf2f2,0xf2f2,gr13
-	test_fr_limmed	0x1111,0x1111,fr40
-	test_fr_limmed	0x1111,0x1111,fr41
-	test_fr_limmed	0x1111,0x1111,fr42
-	test_fr_limmed	0x1111,0x1111,fr43
-
-	; 1 nesr active with the correct address in neear for gr
-	inc_gr_immed	-16,gr12
-	nlddi		@(sp,-16),gr40
-	test_spr_gr	neear2,gr12
-	set_mem_limmed	0x2222,0x2222,gr6
-	set_mem_limmed	0x3333,0x3333,gr27
-	set_mem_limmed	0x4444,0x4444,gr26
-	set_mem_limmed	0x5555,0x5555,gr25
-	set_mem_limmed	0x6666,0x6666,gr24
-	set_mem_limmed	0x7777,0x7777,gr23
-	set_mem_limmed	0x8888,0x8888,gr22
-	set_mem_limmed	0x9999,0x9999,gr21
-	set_mem_limmed	0xaaaa,0xaaaa,gr20
-	set_mem_limmed	0xbbbb,0xbbbb,gr19
-	set_mem_limmed	0xcccc,0xcccc,gr18
-	set_mem_limmed	0xdddd,0xdddd,gr17
-	set_mem_limmed	0xeeee,0xeeee,gr16
-	set_mem_limmed	0xf0f0,0xf0f0,gr15
-	set_mem_limmed	0xf1f1,0xf1f1,gr14
-	set_mem_limmed	0xf2f2,0xf2f2,gr13
-	set_gr_limmed	0xeeee,0xeeee,gr8
-	set_gr_limmed	0xffff,0xffff,gr9
-	set_gr_limmed	0xcccc,0xcccc,gr10
-	set_gr_limmed	0xdddd,0xdddd,gr11
-	set_gr_limmed	0x1111,0x1111,gr40
-	set_gr_limmed	0x1111,0x1111,gr41
-	set_gr_limmed	0x1111,0x1111,gr42
-	set_gr_limmed	0x1111,0x1111,gr43
-	inc_gr_immed	-16,sp
-	set_gr_immed	0,gr7
-	rstq		gr8,@(sp,gr7)
-	test_mem_limmed	0x2222,0x2222,gr6
-	test_mem_limmed	0x3333,0x3333,gr27
-	test_mem_limmed	0x4444,0x4444,gr26
-	test_mem_limmed	0x5555,0x5555,gr25
-	test_mem_limmed	0x6666,0x6666,gr24
-	test_mem_limmed	0x7777,0x7777,gr23
-	test_mem_limmed	0x8888,0x8888,gr22
-	test_mem_limmed	0x9999,0x9999,gr21
-	test_mem_limmed	0xdddd,0xdddd,gr20
-	test_mem_limmed	0xcccc,0xcccc,gr19
-	test_mem_limmed	0xffff,0xffff,gr18
-	test_mem_limmed	0xeeee,0xeeee,gr17
-	test_mem_limmed	0xeeee,0xeeee,gr16
-	test_mem_limmed	0xf0f0,0xf0f0,gr15
-	test_mem_limmed	0xf1f1,0xf1f1,gr14
-	test_mem_limmed	0xf2f2,0xf2f2,gr13
-	test_gr_limmed	0xeeee,0xeeee,gr40
-	test_gr_limmed	0xffff,0xffff,gr41
-	test_gr_limmed	0xcccc,0xcccc,gr42
-	test_gr_limmed	0xdddd,0xdddd,gr43
-
-	; 1 nesr active with the correct address in neear for fr
-	inc_gr_immed	-16,gr12
-	nlddfi		@(sp,-16),fr40
-	test_spr_gr	neear3,gr12
-	set_mem_limmed	0x2222,0x2222,gr6
-	set_mem_limmed	0x3333,0x3333,gr27
-	set_mem_limmed	0x4444,0x4444,gr26
-	set_mem_limmed	0x5555,0x5555,gr25
-	set_mem_limmed	0x6666,0x6666,gr24
-	set_mem_limmed	0x7777,0x7777,gr23
-	set_mem_limmed	0x8888,0x8888,gr22
-	set_mem_limmed	0x9999,0x9999,gr21
-	set_mem_limmed	0xaaaa,0xaaaa,gr20
-	set_mem_limmed	0xbbbb,0xbbbb,gr19
-	set_mem_limmed	0xcccc,0xcccc,gr18
-	set_mem_limmed	0xdddd,0xdddd,gr17
-	set_mem_limmed	0xeeee,0xeeee,gr16
-	set_mem_limmed	0xf0f0,0xf0f0,gr15
-	set_mem_limmed	0xf1f1,0xf1f1,gr14
-	set_mem_limmed	0xf2f2,0xf2f2,gr13
-	set_gr_limmed	0xeeee,0xeeee,gr8
-	set_gr_limmed	0xffff,0xffff,gr9
-	set_gr_limmed	0xcccc,0xcccc,gr10
-	set_gr_limmed	0xdddd,0xdddd,gr11
-	set_fr_iimmed	0x1111,0x1111,fr40
-	set_fr_iimmed	0x1111,0x1111,fr41
-	set_fr_iimmed	0x1111,0x1111,fr42
-	set_fr_iimmed	0x1111,0x1111,fr43
-	set_gr_immed	-16,gr7
-	rstq		gr8,@(sp,gr7)
-	test_mem_limmed	0x2222,0x2222,gr6
-	test_mem_limmed	0x3333,0x3333,gr27
-	test_mem_limmed	0x4444,0x4444,gr26
-	test_mem_limmed	0x5555,0x5555,gr25
-	test_mem_limmed	0x6666,0x6666,gr24
-	test_mem_limmed	0x7777,0x7777,gr23
-	test_mem_limmed	0x8888,0x8888,gr22
-	test_mem_limmed	0x9999,0x9999,gr21
-	test_mem_limmed	0xaaaa,0xaaaa,gr20
-	test_mem_limmed	0xbbbb,0xbbbb,gr19
-	test_mem_limmed	0xcccc,0xcccc,gr18
-	test_mem_limmed	0xdddd,0xdddd,gr17
-	test_mem_limmed	0xdddd,0xdddd,gr16
-	test_mem_limmed	0xcccc,0xcccc,gr15
-	test_mem_limmed	0xffff,0xffff,gr14
-	test_mem_limmed	0xeeee,0xeeee,gr13
-	test_fr_limmed	0xeeee,0xeeee,fr40
-	test_fr_limmed	0xffff,0xffff,fr41
-	test_fr_limmed	0xcccc,0xcccc,fr42
-	test_fr_limmed	0xdddd,0xdddd,fr43
-
-	pass
diff --git a/sim/testsuite/sim/frv/rstqf.cgs b/sim/testsuite/sim/frv/rstqf.cgs
deleted file mode 100644
index 72fd04a..0000000
--- a/sim/testsuite/sim/frv/rstqf.cgs
+++ /dev/null
@@ -1,333 +0,0 @@
-# frv testcase for rstqf $FRk,@($GRi,$GRj)
-# mach: frv
-# as(frv): -mcpu=frv
-
-	.include "testutils.inc"
-
-	start
-
-	.global add
-add:
-	; No nesr's active
-	set_gr_gr	sp,gr12
-	set_mem_limmed	0x2222,0x2222,gr12
-	set_gr_gr	gr12,gr27
-	inc_gr_immed	-4,gr27
-	set_mem_limmed	0x3333,0x3333,gr27
-	set_gr_gr	gr27,gr26
-	inc_gr_immed	-4,gr26
-	set_mem_limmed	0x4444,0x4444,gr26
-	set_gr_gr	gr26,gr25
-	inc_gr_immed	-4,gr25
-	set_mem_limmed	0x5555,0x5555,gr25
-	set_gr_gr	gr25,gr24
-	inc_gr_immed	-4,gr24
-	set_mem_limmed	0x6666,0x6666,gr24
-	set_gr_gr	gr24,gr23
-	inc_gr_immed	-4,gr23
-	set_mem_limmed	0x7777,0x7777,gr23
-	set_gr_gr	gr23,gr22
-	inc_gr_immed	-4,gr22
-	set_mem_limmed	0x8888,0x8888,gr22
-	set_gr_gr	gr22,gr21
-	inc_gr_immed	-4,gr21
-	set_mem_limmed	0x9999,0x9999,gr21
-	set_gr_gr	gr21,gr20
-	inc_gr_immed	-4,gr20
-	set_mem_limmed	0xaaaa,0xaaaa,gr20
-	set_gr_gr	gr20,gr19
-	inc_gr_immed	-4,gr19
-	set_mem_limmed	0xbbbb,0xbbbb,gr19
-	set_gr_gr	gr19,gr18
-	inc_gr_immed	-4,gr18
-	set_mem_limmed	0xcccc,0xcccc,gr18
-	set_gr_gr	gr18,gr17
-	inc_gr_immed	-4,gr17
-	set_mem_limmed	0xdddd,0xdddd,gr17
-	set_gr_gr	gr17,gr16
-	inc_gr_immed	-4,gr16
-	set_mem_limmed	0xeeee,0xeeee,gr16
-	set_gr_gr	gr16,gr15
-	inc_gr_immed	-4,gr15
-	set_mem_limmed	0xf0f0,0xf0f0,gr15
-	set_gr_gr	gr15,gr14
-	inc_gr_immed	-4,gr14
-	set_mem_limmed	0xf1f1,0xf1f1,gr14
-	set_gr_gr	gr14,gr13
-	inc_gr_immed	-4,gr13
-	set_mem_limmed	0xf2f2,0xf2f2,gr13
-	set_gr_limmed	0x1111,0x1111,gr40
-	set_gr_limmed	0x1111,0x1111,gr41
-	set_gr_limmed	0x1111,0x1111,gr42
-	set_gr_limmed	0x1111,0x1111,gr43
-	set_fr_iimmed	0x1111,0x1111,fr40
-	set_fr_iimmed	0x1111,0x1111,fr41
-	set_fr_iimmed	0x1111,0x1111,fr42
-	set_fr_iimmed	0x1111,0x1111,fr43
-	inc_gr_immed	-12,sp
-	set_gr_immed	0,gr7
-	set_fr_iimmed	0xeeee,0xeeee,fr8
-	set_fr_iimmed	0xffff,0xffff,fr9
-	set_fr_iimmed	0xcccc,0xcccc,fr10
-	set_fr_iimmed	0xdddd,0xdddd,fr11
-	rstqf		fr8,@(sp,gr7)
-	test_mem_limmed	0xdddd,0xdddd,gr12
-	test_mem_limmed	0xcccc,0xcccc,gr27
-	test_mem_limmed	0xffff,0xffff,gr26
-	test_mem_limmed	0xeeee,0xeeee,gr25
-	test_mem_limmed	0x6666,0x6666,gr24
-	test_mem_limmed	0x7777,0x7777,gr23
-	test_mem_limmed	0x8888,0x8888,gr22
-	test_mem_limmed	0x9999,0x9999,gr21
-	test_mem_limmed	0xaaaa,0xaaaa,gr20
-	test_mem_limmed	0xbbbb,0xbbbb,gr19
-	test_mem_limmed	0xcccc,0xcccc,gr18
-	test_mem_limmed	0xdddd,0xdddd,gr17
-	test_mem_limmed	0xeeee,0xeeee,gr16
-	test_mem_limmed	0xf0f0,0xf0f0,gr15
-	test_mem_limmed	0xf1f1,0xf1f1,gr14
-	test_mem_limmed	0xf2f2,0xf2f2,gr13
-	test_gr_limmed	0x1111,0x1111,gr40
-	test_gr_limmed	0x1111,0x1111,gr41
-	test_gr_limmed	0x1111,0x1111,gr42
-	test_gr_limmed	0x1111,0x1111,gr43
-	test_fr_limmed	0x1111,0x1111,fr40
-	test_fr_limmed	0x1111,0x1111,fr41
-	test_fr_limmed	0x1111,0x1111,fr42
-	test_fr_limmed	0x1111,0x1111,fr43
-
-	; 1 nesr active with the incorrect address in neear for gr
-	set_gr_gr	sp,gr10
-	inc_gr_immed	-32,gr10
-	set_gr_immed	-32,gr9
-	nldq		@(sp,gr9),gr40
-	test_spr_gr	neear0,gr10
-	set_mem_limmed	0x2222,0x2222,gr12
-	set_mem_limmed	0x3333,0x3333,gr27
-	set_mem_limmed	0x4444,0x4444,gr26
-	set_mem_limmed	0x5555,0x5555,gr25
-	set_mem_limmed	0x6666,0x6666,gr24
-	set_mem_limmed	0x7777,0x7777,gr23
-	set_mem_limmed	0x8888,0x8888,gr22
-	set_mem_limmed	0x9999,0x9999,gr21
-	set_mem_limmed	0xaaaa,0xaaaa,gr20
-	set_mem_limmed	0xbbbb,0xbbbb,gr19
-	set_mem_limmed	0xcccc,0xcccc,gr18
-	set_mem_limmed	0xdddd,0xdddd,gr17
-	set_mem_limmed	0xeeee,0xeeee,gr16
-	set_mem_limmed	0xf0f0,0xf0f0,gr15
-	set_mem_limmed	0xf1f1,0xf1f1,gr14
-	set_mem_limmed	0xf2f2,0xf2f2,gr13
-	set_fr_iimmed	0xeeee,0xeeee,fr8
-	set_fr_iimmed	0xffff,0xffff,fr9
-	set_fr_iimmed	0xcccc,0xcccc,fr10
-	set_fr_iimmed	0xdddd,0xdddd,fr11
-	set_gr_limmed	0x1111,0x1111,gr40
-	set_gr_limmed	0x1111,0x1111,gr41
-	set_gr_limmed	0x1111,0x1111,gr42
-	set_gr_limmed	0x1111,0x1111,gr43
-	set_fr_iimmed	0x1111,0x1111,fr40
-	set_fr_iimmed	0x1111,0x1111,fr41
-	set_fr_iimmed	0x1111,0x1111,fr42
-	set_fr_iimmed	0x1111,0x1111,fr43
-	set_gr_immed	-16,gr7
-	rstqf		fr8,@(sp,gr7)
-	test_mem_limmed	0x2222,0x2222,gr12
-	test_mem_limmed	0x3333,0x3333,gr27
-	test_mem_limmed	0x4444,0x4444,gr26
-	test_mem_limmed	0x5555,0x5555,gr25
-	test_mem_limmed	0xdddd,0xdddd,gr24
-	test_mem_limmed	0xcccc,0xcccc,gr23
-	test_mem_limmed	0xffff,0xffff,gr22
-	test_mem_limmed	0xeeee,0xeeee,gr21
-	test_mem_limmed	0xaaaa,0xaaaa,gr20
-	test_mem_limmed	0xbbbb,0xbbbb,gr19
-	test_mem_limmed	0xcccc,0xcccc,gr18
-	test_mem_limmed	0xdddd,0xdddd,gr17
-	test_mem_limmed	0xeeee,0xeeee,gr16
-	test_mem_limmed	0xf0f0,0xf0f0,gr15
-	test_mem_limmed	0xf1f1,0xf1f1,gr14
-	test_mem_limmed	0xf2f2,0xf2f2,gr13
-	test_gr_limmed	0x1111,0x1111,gr40
-	test_gr_limmed	0x1111,0x1111,gr41
-	test_gr_limmed	0x1111,0x1111,gr42
-	test_gr_limmed	0x1111,0x1111,gr43
-	test_fr_limmed	0x1111,0x1111,fr40
-	test_fr_limmed	0x1111,0x1111,fr41
-	test_fr_limmed	0x1111,0x1111,fr42
-	test_fr_limmed	0x1111,0x1111,fr43
-
-	; 1 nesr active with the incorrect address in neear for fr
-	inc_gr_immed	-16,gr10
-	nlddfi		@(sp,-48),fr40
-	test_spr_gr	neear1,gr10
-	set_mem_limmed	0x2222,0x2222,gr12
-	set_mem_limmed	0x3333,0x3333,gr27
-	set_mem_limmed	0x4444,0x4444,gr26
-	set_mem_limmed	0x5555,0x5555,gr25
-	set_mem_limmed	0x6666,0x6666,gr24
-	set_mem_limmed	0x7777,0x7777,gr23
-	set_mem_limmed	0x8888,0x8888,gr22
-	set_mem_limmed	0x9999,0x9999,gr21
-	set_mem_limmed	0xaaaa,0xaaaa,gr20
-	set_mem_limmed	0xbbbb,0xbbbb,gr19
-	set_mem_limmed	0xcccc,0xcccc,gr18
-	set_mem_limmed	0xdddd,0xdddd,gr17
-	set_mem_limmed	0xeeee,0xeeee,gr16
-	set_mem_limmed	0xf0f0,0xf0f0,gr15
-	set_mem_limmed	0xf1f1,0xf1f1,gr14
-	set_mem_limmed	0xf2f2,0xf2f2,gr13
-	set_fr_iimmed	0xeeee,0xeeee,fr8
-	set_fr_iimmed	0xffff,0xffff,fr9
-	set_fr_iimmed	0xcccc,0xcccc,fr10
-	set_fr_iimmed	0xdddd,0xdddd,fr11
-	set_gr_limmed	0x1111,0x1111,gr40
-	set_gr_limmed	0x1111,0x1111,gr41
-	set_gr_limmed	0x1111,0x1111,gr42
-	set_gr_limmed	0x1111,0x1111,gr43
-	set_fr_iimmed	0x1111,0x1111,fr40
-	set_fr_iimmed	0x1111,0x1111,fr41
-	set_fr_iimmed	0x1111,0x1111,fr42
-	set_fr_iimmed	0x1111,0x1111,fr43
-	inc_gr_immed	-16,sp
-	set_gr_immed	16,gr7
-	rstqf		fr8,@(sp,gr7)
-	test_mem_limmed	0xdddd,0xdddd,gr12
-	test_mem_limmed	0xcccc,0xcccc,gr27
-	test_mem_limmed	0xffff,0xffff,gr26
-	test_mem_limmed	0xeeee,0xeeee,gr25
-	test_mem_limmed	0x6666,0x6666,gr24
-	test_mem_limmed	0x7777,0x7777,gr23
-	test_mem_limmed	0x8888,0x8888,gr22
-	test_mem_limmed	0x9999,0x9999,gr21
-	test_mem_limmed	0xaaaa,0xaaaa,gr20
-	test_mem_limmed	0xbbbb,0xbbbb,gr19
-	test_mem_limmed	0xcccc,0xcccc,gr18
-	test_mem_limmed	0xdddd,0xdddd,gr17
-	test_mem_limmed	0xeeee,0xeeee,gr16
-	test_mem_limmed	0xf0f0,0xf0f0,gr15
-	test_mem_limmed	0xf1f1,0xf1f1,gr14
-	test_mem_limmed	0xf2f2,0xf2f2,gr13
-	test_gr_limmed	0x1111,0x1111,gr40
-	test_gr_limmed	0x1111,0x1111,gr41
-	test_gr_limmed	0x1111,0x1111,gr42
-	test_gr_limmed	0x1111,0x1111,gr43
-	test_fr_limmed	0x1111,0x1111,fr40
-	test_fr_limmed	0x1111,0x1111,fr41
-	test_fr_limmed	0x1111,0x1111,fr42
-	test_fr_limmed	0x1111,0x1111,fr43
-
-	; 1 nesr active with the correct address in neear for gr
-	set_mem_limmed	0x2222,0x2222,gr12
-	set_mem_limmed	0x3333,0x3333,gr27
-	set_mem_limmed	0x4444,0x4444,gr26
-	set_mem_limmed	0x5555,0x5555,gr25
-	set_mem_limmed	0x6666,0x6666,gr24
-	set_mem_limmed	0x7777,0x7777,gr23
-	set_mem_limmed	0x8888,0x8888,gr22
-	set_mem_limmed	0x9999,0x9999,gr21
-	set_mem_limmed	0xaaaa,0xaaaa,gr20
-	set_mem_limmed	0xbbbb,0xbbbb,gr19
-	set_mem_limmed	0xcccc,0xcccc,gr18
-	set_mem_limmed	0xdddd,0xdddd,gr17
-	set_mem_limmed	0xeeee,0xeeee,gr16
-	set_mem_limmed	0xf0f0,0xf0f0,gr15
-	set_mem_limmed	0xf1f1,0xf1f1,gr14
-	set_mem_limmed	0xf2f2,0xf2f2,gr13
-	set_fr_iimmed	0xeeee,0xeeee,fr8
-	set_fr_iimmed	0xffff,0xffff,fr9
-	set_fr_iimmed	0xcccc,0xcccc,fr10
-	set_fr_iimmed	0xdddd,0xdddd,fr11
-	set_gr_limmed	0x1111,0x1111,gr40
-	set_gr_limmed	0x1111,0x1111,gr41
-	set_gr_limmed	0x1111,0x1111,gr42
-	set_gr_limmed	0x1111,0x1111,gr43
-	set_fr_iimmed	0x1111,0x1111,fr40
-	set_fr_iimmed	0x1111,0x1111,fr41
-	set_fr_iimmed	0x1111,0x1111,fr42
-	set_fr_iimmed	0x1111,0x1111,fr43
-	inc_gr_immed	-16,sp
-	set_gr_immed	0,gr7
-	rstqf		fr8,@(sp,gr7)
-	test_mem_limmed	0x2222,0x2222,gr12
-	test_mem_limmed	0x3333,0x3333,gr27
-	test_mem_limmed	0x4444,0x4444,gr26
-	test_mem_limmed	0x5555,0x5555,gr25
-	test_mem_limmed	0x6666,0x6666,gr24
-	test_mem_limmed	0x7777,0x7777,gr23
-	test_mem_limmed	0x8888,0x8888,gr22
-	test_mem_limmed	0x9999,0x9999,gr21
-	test_mem_limmed	0xdddd,0xdddd,gr20
-	test_mem_limmed	0xcccc,0xcccc,gr19
-	test_mem_limmed	0xffff,0xffff,gr18
-	test_mem_limmed	0xeeee,0xeeee,gr17
-	test_mem_limmed	0xeeee,0xeeee,gr16
-	test_mem_limmed	0xf0f0,0xf0f0,gr15
-	test_mem_limmed	0xf1f1,0xf1f1,gr14
-	test_mem_limmed	0xf2f2,0xf2f2,gr13
-	test_gr_limmed	0xeeee,0xeeee,gr40
-	test_gr_limmed	0xffff,0xffff,gr41
-	test_gr_limmed	0xcccc,0xcccc,gr42
-	test_gr_limmed	0xdddd,0xdddd,gr43
-	test_fr_limmed	0x1111,0x1111,fr40
-	test_fr_limmed	0x1111,0x1111,fr41
-	test_fr_limmed	0x1111,0x1111,fr42
-	test_fr_limmed	0x1111,0x1111,fr43
-
-	; 1 nesr active with the correct address in neear for fr
-	set_mem_limmed	0x2222,0x2222,gr12
-	set_mem_limmed	0x3333,0x3333,gr27
-	set_mem_limmed	0x4444,0x4444,gr26
-	set_mem_limmed	0x5555,0x5555,gr25
-	set_mem_limmed	0x6666,0x6666,gr24
-	set_mem_limmed	0x7777,0x7777,gr23
-	set_mem_limmed	0x8888,0x8888,gr22
-	set_mem_limmed	0x9999,0x9999,gr21
-	set_mem_limmed	0xaaaa,0xaaaa,gr20
-	set_mem_limmed	0xbbbb,0xbbbb,gr19
-	set_mem_limmed	0xcccc,0xcccc,gr18
-	set_mem_limmed	0xdddd,0xdddd,gr17
-	set_mem_limmed	0xeeee,0xeeee,gr16
-	set_mem_limmed	0xf0f0,0xf0f0,gr15
-	set_mem_limmed	0xf1f1,0xf1f1,gr14
-	set_mem_limmed	0xf2f2,0xf2f2,gr13
-	set_fr_iimmed	0xeeee,0xeeee,fr8
-	set_fr_iimmed	0xffff,0xffff,fr9
-	set_fr_iimmed	0xcccc,0xcccc,fr10
-	set_fr_iimmed	0xdddd,0xdddd,fr11
-	set_gr_limmed	0x1111,0x1111,gr40
-	set_gr_limmed	0x1111,0x1111,gr41
-	set_gr_limmed	0x1111,0x1111,gr42
-	set_gr_limmed	0x1111,0x1111,gr43
-	set_fr_iimmed	0x1111,0x1111,fr40
-	set_fr_iimmed	0x1111,0x1111,fr41
-	set_fr_iimmed	0x1111,0x1111,fr42
-	set_fr_iimmed	0x1111,0x1111,fr43
-	set_gr_immed	-16,gr7
-	rstqf		fr8,@(sp,gr7)
-	test_mem_limmed	0x2222,0x2222,gr12
-	test_mem_limmed	0x3333,0x3333,gr27
-	test_mem_limmed	0x4444,0x4444,gr26
-	test_mem_limmed	0x5555,0x5555,gr25
-	test_mem_limmed	0x6666,0x6666,gr24
-	test_mem_limmed	0x7777,0x7777,gr23
-	test_mem_limmed	0x8888,0x8888,gr22
-	test_mem_limmed	0x9999,0x9999,gr21
-	test_mem_limmed	0xaaaa,0xaaaa,gr20
-	test_mem_limmed	0xbbbb,0xbbbb,gr19
-	test_mem_limmed	0xcccc,0xcccc,gr18
-	test_mem_limmed	0xdddd,0xdddd,gr17
-	test_mem_limmed	0xdddd,0xdddd,gr16
-	test_mem_limmed	0xcccc,0xcccc,gr15
-	test_mem_limmed	0xffff,0xffff,gr14
-	test_mem_limmed	0xeeee,0xeeee,gr13
-	test_gr_limmed	0x1111,0x1111,gr40
-	test_gr_limmed	0x1111,0x1111,gr41
-	test_gr_limmed	0x1111,0x1111,gr42
-	test_gr_limmed	0x1111,0x1111,gr43
-	test_fr_limmed	0xeeee,0xeeee,fr40
-	test_fr_limmed	0xffff,0xffff,fr41
-	test_fr_limmed	0xcccc,0xcccc,fr42
-	test_fr_limmed	0xdddd,0xdddd,fr43
-
-	pass
author	Richard Sandiford <rdsandiford@googlemail.com>	2004-03-01 09:26:33 +0000
committer	Richard Sandiford <rdsandiford@googlemail.com>	2004-03-01 09:26:33 +0000
commit	8ae0baa2685df96375cc43b44b5632044288f74a (patch)
tree	f66d697cb45e2fb7bb61ddd1e25047cfd75f4e65 /sim
parent	3ce2bf1815f79e33ffbcebcf7da5f6896536f390 (diff)
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