diff options
| author | Chris Demetriou <cgd@google.com> | 2002-02-28 07:01:14 +0000 |
|---|---|---|
| committer | Chris Demetriou <cgd@google.com> | 2002-02-28 07:01:14 +0000 |
| commit | af5107af975bcf912be1187f4210706db408dabe (patch) | |
| tree | 0aced11aec5d6986758e26a69129a58a777ed2be /sim | |
| parent | 3422b41a7413161dcb5e2cffbd7ea532c32119ab (diff) | |
| download | fsf-binutils-gdb-af5107af975bcf912be1187f4210706db408dabe.zip fsf-binutils-gdb-af5107af975bcf912be1187f4210706db408dabe.tar.gz fsf-binutils-gdb-af5107af975bcf912be1187f4210706db408dabe.tar.bz2 | |
2002-02-27 Chris Demetriou <cgd@broadcom.com>
* mips.igen (PREFX): Tweak instruction opcode fields (i.e.,
add a comma) so that it more closely match the MIPS ISA
documentation opcode partitioning.
(PREF): Put useful names on opcode fields, and include
instruction-printing string.
Diffstat (limited to 'sim')
| -rw-r--r-- | sim/mips/ChangeLog | 8 | ||||
| -rw-r--r-- | sim/mips/mips.igen | 5 |
2 files changed, 11 insertions, 2 deletions
diff --git a/sim/mips/ChangeLog b/sim/mips/ChangeLog index 9083040..4789ba9 100644 --- a/sim/mips/ChangeLog +++ b/sim/mips/ChangeLog @@ -1,5 +1,13 @@ 2002-02-27 Chris Demetriou <cgd@broadcom.com> + * mips.igen (PREFX): Tweak instruction opcode fields (i.e., + add a comma) so that it more closely match the MIPS ISA + documentation opcode partitioning. + (PREF): Put useful names on opcode fields, and include + instruction-printing string. + +2002-02-27 Chris Demetriou <cgd@broadcom.com> + * mips.igen (check_u64): New function which in the future will check whether 64-bit instructions are usable and signal an exception if not. Currently a no-op. diff --git a/sim/mips/mips.igen b/sim/mips/mips.igen index 72626d2..d19ac97 100644 --- a/sim/mips/mips.igen +++ b/sim/mips/mips.igen @@ -2083,7 +2083,8 @@ } -110011,5.RS,nnnnn,16.OFFSET:NORMAL:32::PREF +110011,5.BASE,5.HINT,16.OFFSET:NORMAL:32::PREF +"pref <HINT>, <OFFSET>(r<BASE>)" *mipsIV: *mipsV: *vr5000: @@ -3974,7 +3975,7 @@ } -010011,5.BASE,5.INDEX,5.HINT,00000001111:COP1X:32::PREFX +010011,5.BASE,5.INDEX,5.HINT,00000,001111:COP1X:32::PREFX "prefx <HINT>, r<INDEX>(r<BASE>)" *mipsIV: *mipsV: |