From af5107af975bcf912be1187f4210706db408dabe Mon Sep 17 00:00:00 2001 From: Chris Demetriou Date: Thu, 28 Feb 2002 07:01:14 +0000 Subject: 2002-02-27 Chris Demetriou * mips.igen (PREFX): Tweak instruction opcode fields (i.e., add a comma) so that it more closely match the MIPS ISA documentation opcode partitioning. (PREF): Put useful names on opcode fields, and include instruction-printing string. --- sim/mips/ChangeLog | 8 ++++++++ sim/mips/mips.igen | 5 +++-- 2 files changed, 11 insertions(+), 2 deletions(-) (limited to 'sim') diff --git a/sim/mips/ChangeLog b/sim/mips/ChangeLog index 9083040..4789ba9 100644 --- a/sim/mips/ChangeLog +++ b/sim/mips/ChangeLog @@ -1,5 +1,13 @@ 2002-02-27 Chris Demetriou + * mips.igen (PREFX): Tweak instruction opcode fields (i.e., + add a comma) so that it more closely match the MIPS ISA + documentation opcode partitioning. + (PREF): Put useful names on opcode fields, and include + instruction-printing string. + +2002-02-27 Chris Demetriou + * mips.igen (check_u64): New function which in the future will check whether 64-bit instructions are usable and signal an exception if not. Currently a no-op. diff --git a/sim/mips/mips.igen b/sim/mips/mips.igen index 72626d2..d19ac97 100644 --- a/sim/mips/mips.igen +++ b/sim/mips/mips.igen @@ -2083,7 +2083,8 @@ } -110011,5.RS,nnnnn,16.OFFSET:NORMAL:32::PREF +110011,5.BASE,5.HINT,16.OFFSET:NORMAL:32::PREF +"pref , (r)" *mipsIV: *mipsV: *vr5000: @@ -3974,7 +3975,7 @@ } -010011,5.BASE,5.INDEX,5.HINT,00000001111:COP1X:32::PREFX +010011,5.BASE,5.INDEX,5.HINT,00000,001111:COP1X:32::PREFX "prefx , r(r)" *mipsIV: *mipsV: -- cgit v1.1