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| author | Sergio Durigan Junior <sergiodj@redhat.com> | 2013-10-09 21:42:11 +0000 |
|---|---|---|
| committer | Sergio Durigan Junior <sergiodj@redhat.com> | 2013-10-09 21:42:11 +0000 |
| commit | 40776d192726ae0ed6fde0e9f29f0a9ad52f748b (patch) | |
| tree | 39524163d11320ef79265484e674277dbb1a9516 /sim | |
| parent | 9a757e4d208a78cb1c2e51d7804f5214bee8d50f (diff) | |
| download | fsf-binutils-gdb-40776d192726ae0ed6fde0e9f29f0a9ad52f748b.zip fsf-binutils-gdb-40776d192726ae0ed6fde0e9f29f0a9ad52f748b.tar.gz fsf-binutils-gdb-40776d192726ae0ed6fde0e9f29f0a9ad52f748b.tar.bz2 | |
sim/erc32/ChangeLog:
2013-10-09 Sergio Durigan Junior <sergiodj@redhat.com>
PR sim/16018:
* float.c (set_fsr): Add missing "break" statements. Reindent
code.
Diffstat (limited to 'sim')
| -rw-r--r-- | sim/erc32/ChangeLog | 6 | ||||
| -rw-r--r-- | sim/erc32/float.c | 13 |
2 files changed, 16 insertions, 3 deletions
diff --git a/sim/erc32/ChangeLog b/sim/erc32/ChangeLog index 4fff0da..d7266fd 100644 --- a/sim/erc32/ChangeLog +++ b/sim/erc32/ChangeLog @@ -1,3 +1,9 @@ +2013-10-09 Sergio Durigan Junior <sergiodj@redhat.com> + + PR sim/16018: + * float.c (set_fsr): Add missing "break" statements. Reindent + code. + 2013-09-23 Alan Modra <amodra@gmail.com> * configure: Regenerate. diff --git a/sim/erc32/float.c b/sim/erc32/float.c index c1a46f8..1b8f0fc 100644 --- a/sim/erc32/float.c +++ b/sim/erc32/float.c @@ -91,9 +91,16 @@ uint32 fsr; fsr >>= 30; switch (fsr) { case 0: - case 2: break; - case 1: fsr = 3; - case 3: fsr = 1; + case 2: + break; + + case 1: + fsr = 3; + break; + + case 3: + fsr = 1; + break; } rawfsr = _get_cw(); rawfsr |= (fsr << 10) | 0x3ff; |