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author | Mike Frysinger <vapier@gentoo.org> | 2021-01-05 22:09:57 -0500 |
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committer | Mike Frysinger <vapier@gentoo.org> | 2021-01-15 19:18:34 -0500 |
commit | 1368b914e93a3af332f787d3d41c106d11bb90da (patch) | |
tree | 9893ccae5d2d8cbf2ce855e09d6b8f30b56a21bc /sim/testsuite/cris/asm/rfe.ms | |
parent | e403a898b5893337baea73bcb001ece74042f351 (diff) | |
download | fsf-binutils-gdb-1368b914e93a3af332f787d3d41c106d11bb90da.zip fsf-binutils-gdb-1368b914e93a3af332f787d3d41c106d11bb90da.tar.gz fsf-binutils-gdb-1368b914e93a3af332f787d3d41c106d11bb90da.tar.bz2 |
sim: testsuite: flatten tree
Now that all port tests live under testsuite/sim/*/, and none live
in testsuite/ directly, flatten the structure by moving all of the
dirs under testsuite/sim/ to testsuite/ directly.
We need to stop passing --tool to dejagnu so that it searches all
dirs and not just ones that start with "sim". Since we have no
other dirs in this tree, and no plans to add any, should be fine.
Diffstat (limited to 'sim/testsuite/cris/asm/rfe.ms')
-rw-r--r-- | sim/testsuite/cris/asm/rfe.ms | 47 |
1 files changed, 47 insertions, 0 deletions
diff --git a/sim/testsuite/cris/asm/rfe.ms b/sim/testsuite/cris/asm/rfe.ms new file mode 100644 index 0000000..8d53778 --- /dev/null +++ b/sim/testsuite/cris/asm/rfe.ms @@ -0,0 +1,47 @@ +# mach: crisv32 +# output: 4000c3af\n40000020\n40000080\n40000000\n + +; Check that RFE affects CCS the right way. + + .include "testutils.inc" + start + +; Set SPC to 1 to disable single step exceptions when S flag is set. + move 1,spc + +; CCS: +; 31 24 23 16 15 8 7 0 +; +---+-----------+-------+-------+-----------+---+---------------+ +; |Q M|S R P U I X N Z V C|S R P U I X N Z V C|S R P U I X N Z V C| +; | |2 2 2 2 2 2 2 2 2 2|1 1 1 1 1 1 1 1 1 1| | +; +---+-----------+-------+-------+-----------+---+---------------+ + +; Clear S R P U I X N Z V C, set S1 R1 P1 (not U1) I1 X1 N1 Z1 V1 C1, +; clear S2 R2 P2 U2 N2 Z2 V2 C2, Q; set I2 X2 M: +; 1 1 0 0 0 0 1 1 0 0 0 0 1 1 1 0 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 + move 0x430efc00,ccs + + test_cc 0 0 0 0 + + rfe + test_cc 1 1 1 1 + move ccs,r3 + dumpr3 ; 0x4000c3af + + rfe + test_cc 0 0 0 0 + move ccs,r3 + dumpr3 ; 0x40000020 + + rfe + test_cc 0 0 0 0 + move ccs,r3 + dumpr3 ; 0x40000080 + + or.w 0x100,r3 + move $r3,ccs + rfe + move ccs,r3 + dumpr3 ; 0x40000000 + + quit |