[sim] Run spellcheck.sh in sim (part 1)

Run gdb/contrib/spellcheck.sh on directory sim.

Fix auto-corrected typos:
...
accessable -> accessible
accidently -> accidentally
accomodate -> accommodate
adress -> address
afair -> affair
agains -> against
agressively -> aggressively
annuled -> annulled
arbitary -> arbitrary
arround -> around
auxillary -> auxiliary
availablity -> availability
clasic -> classic
comming -> coming
controled -> controlled
controling -> controlling
destory -> destroy
existance -> existence
explictly -> explicitly
faciliate -> facilitate
fouth -> fourth
fullfilled -> fulfilled
guarentee -> guarantee
hinderance -> hindrance
independant -> independent
inital -> initial
loosing -> losing
occurance -> occurrence
occured -> occurred
occuring -> occurring
omited -> omitted
oportunity -> opportunity
parallely -> parallelly
permissable -> permissible
postive -> positive
powerfull -> powerful
preceed -> precede
preceeding -> preceding
preceeds -> precedes
primative -> primitive
probaly -> probably
programable -> programmable
propogate -> propagate
propper -> proper
recieve -> receive
reconized -> recognized
refered -> referred
refering -> referring
relevent -> relevant
responisble -> responsible
retreive -> retrieve
safty -> safety
specifiying -> specifying
spontanous -> spontaneous
sqaure -> square
successfull -> successful
supress -> suppress
sytem -> system
thru -> through
transfered -> transferred
trigered -> triggered
unfortunatly -> unfortunately
upto -> up to
usefull -> useful
wierd -> weird
writen -> written
doesnt -> doesn't
isnt -> isn't
...

Manually undid the "andd -> and" transformation in sim/testsuite/cr16/andd.cgs
and sim/cr16/simops.c.

Tested by rebuilding on x86_64-linux.

Approved-By: Tom Tromey <tom@tromey.com>

1 files changed, 3 insertions, 3 deletions

diff --git a/sim/sh/interp.c b/sim/sh/interp.c
index bbf26bb..379b44f 100644
--- a/sim/sh/interp.c
+++ b/sim/sh/interp.c
@@ -146,7 +146,7 @@ static int maskl = 0;
 
 /* Alternate bank of registers r0-r7 */
 
-/* Note: code controling SR handles flips between BANK0 and BANK1 */
+/* Note: code controlling SR handles flips between BANK0 and BANK1 */
 #define Rn_BANK(n) (saved_state.asregs.bank[(n)])
 #define SET_Rn_BANK(n, EXP) do { saved_state.asregs.bank[(n)] = (EXP); } while (0)
 
@@ -726,7 +726,7 @@ static int nsamples;
 #define SSR1 (0x05FFFECC)	/* Channel 1  serial status register */
 #define RDR1 (0x05FFFECD)	/* Channel 1  receive data register */
 
-#define SCI_RDRF  	 0x40	/* Recieve data register full */
+#define SCI_RDRF  	 0x40	/* Receive data register full */
 #define SCI_TDRE	0x80	/* Transmit data register empty */
 
 static int
@@ -1238,7 +1238,7 @@ macl (int *regs, unsigned char *memory, int n, int m)
           mach |= 0xffff8000; /* Sign extend higher 16 bits */
         }
       else
-        mach = mach & 0x00007fff; /* Postive Result */
+        mach = mach & 0x00007fff; /* Positive Result */
     }
 
   MACL = macl;