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| author | Jim Wilson <jim.wilson@linaro.org> | 2017-01-04 16:05:27 -0800 |
|---|---|---|
| committer | Jim Wilson <jim.wilson@linaro.org> | 2017-01-04 16:07:50 -0800 |
| commit | c0386d4d54d2cc33d6efc0b998fe6396bf92be15 (patch) | |
| tree | e97b96bb8f66695fa61e97fc61587b25881a19c7 /sim/aarch64/cpustate.c | |
| parent | 6ed0191f6582a3b008277f0d2dc18d6764313ac5 (diff) | |
| download | fsf-binutils-gdb-c0386d4d54d2cc33d6efc0b998fe6396bf92be15.zip fsf-binutils-gdb-c0386d4d54d2cc33d6efc0b998fe6396bf92be15.tar.gz fsf-binutils-gdb-c0386d4d54d2cc33d6efc0b998fe6396bf92be15.tar.bz2 | |
Five fixes, for fcsel, fcvtz, fminnm, mls, and non-widening mul.
sim/aarch64/
* cpustate.c: Include math.h.
(aarch64_set_FP_float): Use signbit to check for signed zero.
(aarch64_set_FP_double): Likewise.
* simulator.c (do_vec_MOV_immediate, case 0x8): Add missing break.
(do_vec_mul): In all DO_VEC_WIDENING_MUL calls, make second and fourth
args same size as third arg.
(fmaxnm): Use isnan instead of fpclassify.
(fminnm, dmaxnm, dminnm): Likewise.
(do_vec_MLS): Reverse order of subtraction operands.
(dexSimpleFPCondSelect): Call aarch64_get_FP_double or
aarch64_get_FP_float to get source register contents.
(UINT_MIN, ULONG_MIN, FLOAT_UINT_MAX, FLOAT_UINT_MIN,
DOUBLE_UINT_MAX, DOUBLE_UINT_MIN, FLOAT_ULONG_MAX, FLOAT_ULONG_MIN,
DOUBLE_ULONG_MAX, DOUBLE_ULONG_MIN): New.
(do_fcvtzu): Use ULONG instead of LONG, and UINT instead of INT in
raise_exception calls.
sim/testsuite/sim/aarch64/
* fcsel.s: New.
* fcvtz.s: New.
* fminnm.s: New.
* mls.s: New.
* mul.s: New.
Diffstat (limited to 'sim/aarch64/cpustate.c')
| -rw-r--r-- | sim/aarch64/cpustate.c | 9 |
1 files changed, 7 insertions, 2 deletions
diff --git a/sim/aarch64/cpustate.c b/sim/aarch64/cpustate.c index 7975b32..b7ea5d4 100644 --- a/sim/aarch64/cpustate.c +++ b/sim/aarch64/cpustate.c @@ -20,6 +20,7 @@ along with this program. If not, see <http://www.gnu.org/licenses/>. */ #include <stdio.h> +#include <math.h> #include "sim-main.h" #include "cpustate.h" @@ -369,7 +370,9 @@ aarch64_set_FP_half (sim_cpu *cpu, VReg reg, float val) void aarch64_set_FP_float (sim_cpu *cpu, VReg reg, float val) { - if (val != cpu->fr[reg].s) + if (val != cpu->fr[reg].s + /* Handle +/- zero. */ + || signbit (val) != signbit (cpu->fr[reg].s)) { FRegister v; @@ -385,7 +388,9 @@ aarch64_set_FP_float (sim_cpu *cpu, VReg reg, float val) void aarch64_set_FP_double (sim_cpu *cpu, VReg reg, double val) { - if (val != cpu->fr[reg].d) + if (val != cpu->fr[reg].d + /* Handle +/- zero. */ + || signbit (val) != signbit (cpu->fr[reg].d)) { FRegister v; |