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| author | Carlo Bramini <carlo_bramini@users.sourceforge.net> | 2020-02-06 22:50:26 +0000 |
|---|---|---|
| committer | Andrew Burgess <andrew.burgess@embecosm.com> | 2020-02-06 22:50:26 +0000 |
| commit | 69b1ffdb01106ed84a41a80f6ad2d9c26c4f45a9 (patch) | |
| tree | 284c914e9ea392b7d0c682e09a9838d0b53b6f30 /sim/aarch64/ChangeLog | |
| parent | 1d5d29e73f4b5f1af4df5b6e39ccf2fa722acead (diff) | |
| download | fsf-binutils-gdb-69b1ffdb01106ed84a41a80f6ad2d9c26c4f45a9.zip fsf-binutils-gdb-69b1ffdb01106ed84a41a80f6ad2d9c26c4f45a9.tar.gz fsf-binutils-gdb-69b1ffdb01106ed84a41a80f6ad2d9c26c4f45a9.tar.bz2 | |
sim/aarch64: Fix register ordering bug in blr (PR sim/25318)
A comment in the implementation of blr says:
/* The pseudo code in the spec says we update LR before fetching.
the value from the rn. */
With 'rn' being the register holding the destination address.
This may have been true at one point, but the ISA manual now clearly
shows the destination register being read before the link register is
written.
This commit updates the implementation of blr to match.
sim/aarch64/ChangeLog:
PR sim/25318
* simulator.c (blr): Read destination register before calling
aarch64_save_LR.
Change-Id: Icb1c556064e3d9c807ac28440475caa205ab1064
Diffstat (limited to 'sim/aarch64/ChangeLog')
| -rw-r--r-- | sim/aarch64/ChangeLog | 6 |
1 files changed, 6 insertions, 0 deletions
diff --git a/sim/aarch64/ChangeLog b/sim/aarch64/ChangeLog index 9ab81ad..1b907b9 100644 --- a/sim/aarch64/ChangeLog +++ b/sim/aarch64/ChangeLog @@ -1,3 +1,9 @@ +2020-02-06 Carlo Bramini <carlo_bramini@users.sourceforge.net> + + PR sim/25318 + * simulator.c (blr): Read destination register before calling + aarch64_save_LR. + 2019-03-28 Andrew Burgess <andrew.burgess@embecosm.com> * cpustate.c: Add 'libiberty.h' include. |