From 69b1ffdb01106ed84a41a80f6ad2d9c26c4f45a9 Mon Sep 17 00:00:00 2001 From: Carlo Bramini Date: Thu, 6 Feb 2020 22:50:26 +0000 Subject: sim/aarch64: Fix register ordering bug in blr (PR sim/25318) A comment in the implementation of blr says: /* The pseudo code in the spec says we update LR before fetching. the value from the rn. */ With 'rn' being the register holding the destination address. This may have been true at one point, but the ISA manual now clearly shows the destination register being read before the link register is written. This commit updates the implementation of blr to match. sim/aarch64/ChangeLog: PR sim/25318 * simulator.c (blr): Read destination register before calling aarch64_save_LR. Change-Id: Icb1c556064e3d9c807ac28440475caa205ab1064 --- sim/aarch64/ChangeLog | 6 ++++++ 1 file changed, 6 insertions(+) (limited to 'sim/aarch64/ChangeLog') diff --git a/sim/aarch64/ChangeLog b/sim/aarch64/ChangeLog index 9ab81ad..1b907b9 100644 --- a/sim/aarch64/ChangeLog +++ b/sim/aarch64/ChangeLog @@ -1,3 +1,9 @@ +2020-02-06 Carlo Bramini + + PR sim/25318 + * simulator.c (blr): Read destination register before calling + aarch64_save_LR. + 2019-03-28 Andrew Burgess * cpustate.c: Add 'libiberty.h' include. -- cgit v1.1