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| author | Christoph Müllner <christoph.muellner@vrull.eu> | 2022-06-21 15:30:56 +0200 |
|---|---|---|
| committer | Philipp Tomsich <philipp.tomsich@vrull.eu> | 2022-09-23 19:51:29 +0200 |
| commit | eb668e50036e979fb0a74821df4eee0307b44e66 (patch) | |
| tree | 11c176f3cbe8b76ecfe95258ab963bdbc69832e0 /opcodes | |
| parent | 618ba27878a2c6f155eb5e1235c0484a55786a15 (diff) | |
| download | fsf-binutils-gdb-eb668e50036e979fb0a74821df4eee0307b44e66.zip fsf-binutils-gdb-eb668e50036e979fb0a74821df4eee0307b44e66.tar.gz fsf-binutils-gdb-eb668e50036e979fb0a74821df4eee0307b44e66.tar.bz2 | |
RISC-V: Add Zawrs ISA extension support
This patch adds support for the Zawrs ISA extension
("wrs.nto" and "wrs.sto" instructions).
The specification can be found here:
https://github.com/riscv/riscv-zawrs/blob/main/zawrs.adoc
Signed-off-by: Christoph Müllner <christoph.muellner@vrull.eu>
Diffstat (limited to 'opcodes')
| -rw-r--r-- | opcodes/riscv-opc.c | 4 |
1 files changed, 4 insertions, 0 deletions
diff --git a/opcodes/riscv-opc.c b/opcodes/riscv-opc.c index c1bcdb7..83fcc68 100644 --- a/opcodes/riscv-opc.c +++ b/opcodes/riscv-opc.c @@ -950,6 +950,10 @@ const struct riscv_opcode riscv_opcodes[] = {"cbo.inval", 0, INSN_CLASS_ZICBOM, "0(s)", MATCH_CBO_INVAL, MASK_CBO_INVAL, match_opcode, 0 }, {"cbo.zero", 0, INSN_CLASS_ZICBOZ, "0(s)", MATCH_CBO_ZERO, MASK_CBO_ZERO, match_opcode, 0 }, +/* Zawrs instructions. */ +{"wrs.nto", 0, INSN_CLASS_ZAWRS, "", MATCH_WRS_NTO, MASK_WRS_NTO, match_opcode, 0 }, +{"wrs.sto", 0, INSN_CLASS_ZAWRS, "", MATCH_WRS_STO, MASK_WRS_STO, match_opcode, 0 }, + /* Zbb or zbkb instructions. */ {"clz", 0, INSN_CLASS_ZBB, "d,s", MATCH_CLZ, MASK_CLZ, match_opcode, 0 }, {"ctz", 0, INSN_CLASS_ZBB, "d,s", MATCH_CTZ, MASK_CTZ, match_opcode, 0 }, |